Google reviews five TPU generations: an architecture set in 2017 survived the Transformer takeover and scaled 3600x. For optical readers, the key line: OCS, one of only two designs still unique to TPU, is what keeps a near-10K-chip machine alive, schedulable and deployable in stages. Power has now replaced cost as the new ceiling.

At FMS 2026 Marvell unveiled a trio of memory products, and the market read it as another wave of AI launches. Put them in the context of four acquisitions, though, and the real play is owning the entire "data movement layer" — memory is just the first toll. We break down the map, the moat and the supply chain positioning.

imec pushed 3D-stacking hybrid bonding to a 200 nm pitch, but the real message is that the deciding factor has moved from bonding to overlay, CMP and pad design. Why is 200 nm a yield cliff, why are overlay accuracy and electrical yield locked in a linear relationship, and where is the next bottleneck for AI 3D integration?

W2W Cu-Cu hybrid bonding pushed to 450 nm pitch for the first time while holding high yield (98%/100% across 20 million interconnects). Applied Materials traced the yield killer to residual BTA carbon at the bond interface and engineered the interface chemistry, barrier and anneal — groundwork for 3D DRAM and HBM.

Today a rack draws 120 kW; the next generation will exceed 0.5 MW. At ECOC 2026, Microsoft asked a true customer's question: if optics were cheap enough, why keep this architecture? The answer came as a five-number spec sheet, plus a declaration that the die, not the package, is now the unit of design, assembly and failure.

Who wins the AI chip race barely matters to Advantest — GPUs, custom ASICs and CPUs all end up on the same V93000. Operating margin hit 51.7% this quarter, full-year guidance was raised sharply, and demand visibility now stretches to 18 months. Memory and DRAM costs are the only headwind worth watching.

TSMC's 3DIC talk at OCP carried one real message: component-level qualification is dead. With customer chips entering the fab before TSMC's own test vehicles, packaging has become the gatekeeper of AI compute, and TSMC wants the whole supply chain inside STCO. Its line that 'signaling belongs to photons' is a direct endorsement of CPO and silicon photonics.

AI's performance bottleneck is no longer compute but data movement across chips and packages. At VLSI 2026, TSMC answered with its 3DFabric platform: make the package itself the vehicle for AI scaling. We walk through all 19 figures, from 48x compute and 34x HBM bandwidth to power-thermal co-optimization and agentic EDA.