OCP Global Summit 2026 | Avicena | Nigel Alvares | µLED Interconnects for Scale-In and Scale-Up

1. Why Avicena Is the One Making This Case

The talk sat in the OCP Global Summit "Special Focus: Photonics" track. Alvares opened by thanking Credo for the "wider, slower, and better" slogan, a tacit admission that several companies are now competing to own the slow-and-wide narrative at this summit.

He split AI scaling into four directions: scale-across (hundreds to thousands of kilometers), scale-out (meters to kilometers), scale-up (about 10 m for inference, up to 50 m for training) and scale-in (millimeters to 1 m, chip-to-chip and chip-to-memory). The first two are optical territory today; the last two belong to copper. Avicena is going after the last two, and says plainly that µLED targets copper replacement only within 10 m, leaving longer reaches to other technologies.

That self-imposed limit matters. In STT's read of Credo's talk at the same summit, the 50 m active optical cable falls in the micro-VCSEL column (Credo calls it micro-pixel on stage). The µLED camp itself has narrowed the battlefield to inside the rack and inside the package.

2. Breaking Down Avicena's Argument: Optics Lose on Seven Things Other Than Reach

Avicena's comparison table is blunt: optics win on reach but lose to copper on every other requirement.

Requirement	Current optical solutions	Avicena µLED claim
Bandwidth density	Shoreline-limited	>10 Tbps/mm shoreline, >10 Tbps/mm² area
Reliability	Laser-limited, needs a complex external light source	No lasers, array spare-lane redundancy
Power	>10 pJ/bit (incl. >5 pJ/bit host SerDes)	<1 pJ/bit, no threshold current
Latency	DSP retiming and higher-order modulation	NRZ native, no SerDes, DSP, PAM4/PAM6
Temperature	Laser-limited	>200°C
Silicon integration	Multiple non-silicon components	Wafer-level processing, simple transfer processes
Cost	Far above $0.10 per Gbps	Below $0.10 per Gbps

The speaker added on stage that current solutions run about $0.50 per Gbps and up. For one 6.4T endpoint, $0.10 per Gbps is $640 and $0.50 is $3,200 (STT calculation). Power scales the same way: 6.4T at 10 pJ/bit is 64 W, at 1 pJ/bit only 6.4 W.

The numbers look great, but every cell in the right-hand column shares one assumption: there is no SerDes in the link.

3. Breaking Down the Architecture: Remove the SerDes from the Die Edge

Avicena makes the point with two side-by-side diagrams. Inside today's XPU, compute cores, HBM controllers and PCIe controllers run wide parallel data paths in a roughly 1–4 GHz clock domain; at the die edge, a large SerDes block serializes those signals into high-speed serial lanes. That SerDes costs area, burns power and adds latency.

▲ Avicena proposes replacing scale-up SerDes at the XPU edge with wide-and-slow 1–8 Gbps µLED optical I/O, saving power, latency and cost and escaping the chip-edge length limit (Image source: Avicena | 2026 OCP Global Summit presentation)

Avicena's proposal is to drive the parallel data straight onto a µLED array through drivers and TIAs, with no serialization. Because µLEDs form a 2D array, bandwidth is no longer bounded by shoreline length and can be counted by area. The speaker said the XPU side can attach via a die-to-die chiplet or be integrated directly into the XPU silicon; on the switch side, the I/O blocks around a chip like Tomahawk are swapped out, with fiber bundles or multicore fiber in between.

Put simply: Avicena is not selling an optical module, it is selling a new chip I/O architecture. The speaker himself said that to get µLED's value you have to get rid of the SerDes. The implication is that the people who must change their designs are not module makers but XPU and switch chip architects. That matches our conclusion in ECOC2026 | Fast-narrow vs slow-wide: scale-up optics is decided at the SerDes on the die edge.

4. Products and Roadmap: Starting with AOCs Means Plugging the SerDes Back In

What Avicena ships today is the LightBundle 1 Tbps evaluation kit (eKit): 335 µLED channels at 3 Gbps each, with a 12 nm ASIC integrating 300+ drivers and TIAs, delivering more than 1 Tbps from about 1 mm² of µLED array. On the PD side it works with TSMC, optimizing a CMOS image sensor process; the µLED epitaxy is designed in Avicena's own nanofab.

▲ LightBundle 1 Tbps ASIC and evaluation kit: 335 µLED channels at 3 Gbps each, delivering over 1 Tbps from an array of about 1 mm² (Image source: Avicena | 2026 OCP Global Summit presentation)

The roadmap has three stages:

• Shipping: 1 Tbps eKit for customer evaluation and µLED array reliability testing

• Coming soon: 1.6T to 6.4T scale-up optical engines, expected next year per the speaker, starting with AOCs to open the market and win hyperscaler qualification

• Future: purpose-built NPO/CPO optical engines for scale-up and scale-in

▲ Avicena roadmap: the shipping 1 Tbps eKit, upcoming 1.6T–6.4T optical engines, and future NPO/CPO (Image source: Avicena | 2026 OCP Global Summit presentation)

This is the contradiction most worth unpacking. The speaker did not specify the AOC's electrical interface, but STT infers that an AOC plugging into existing switches and XPUs must present 100G/200G-class PAM4 SerDes; the µLED side runs 3 Gbps NRZ, so a gearbox is required in between. At 3 Gbps per channel, 1.6T needs about 533 channels and 6.4T about 2,133 (per direction, before spares; STT calculation).

By Avicena's own breakdown on slide 5, the host SerDes alone exceeds 5 pJ/bit. As long as the SerDes stays, system energy can at best fall from >10 pJ/bit to around 6 pJ/bit (>5 pJ/bit host SerDes plus <1 pJ/bit µLED, before gearbox power), an improvement of at most about 40%, not the ~90% implied by <1 pJ/bit (STT estimate).

▲ By Avicena's own breakdown, a µLED AOC that keeps the host SerDes is about 6 pJ/bit; only a native wide interface without SerDes reaches <1 pJ/bit (Image source: Simple Tech Trend original; data from Avicena 2026 OCP Global Summit presentation)

That does not make the AOC a wrong strategy. The speaker was clear that this step is about hyperscaler qualification. But readers should keep the distinction: the µLED products arriving next year will sell on reach, weight and temperature tolerance, not on <1 pJ/bit.

5. Breaking Down Density: 10 Tbps/mm² Is the Display Pixel-Pitch Roadmap

Today's eKit is about 1 Tbps/mm²; the target is >10 Tbps/mm², a 10x gap. At 3 Gbps per channel, 10 Tbps/mm² needs about 3,333 channels per mm², an equivalent pitch of about 17 µm; at 8 Gbps per channel it needs about 1,250 channels, a pitch of about 28 µm. Today's 335 channels work out to about 55 µm (idealized, ignoring the Tx/Rx split and spares).

▲ Going from about 1 Tbps/mm² to >10 Tbps/mm² requires shrinking the effective µLED pitch from about 55 µm to 17–28 µm (Image source: Simple Tech Trend original; data from Avicena 2026 OCP Global Summit presentation)

The speaker said on stage that µLED pitch will follow AR/VR displays below 30 µm and later below 20 µm (these numbers are not on the slides), contrasting it with about 50 µm for micro-VCSELs (which he called micro-pixels). This is µLED's strongest argument against micro-VCSELs: the display industry is paying for pitch shrink. Microsoft also published its own optical I/O targets at ECOC (see ECOC2026 | Microsoft wrote down the spec sheet for optical I/O), and Avicena's density targets can be read directly against them.

6. Risks and Counterarguments

• Reliability is still unproven. In Q&A the speaker acknowledged that the hardest part was making µLEDs, never designed for high speed, run fast, and that proving reliability comes next; the eKit itself is labeled for µLED array reliability testing.

• Fiber count is slow-and-wide's old problem. More than 2,000 channels must be carried on fiber bundles or multicore fiber, exactly the bottleneck described in What kills slow-and-wide is not physics but 60,000 fibers. Avicena gave no fiber or connector cost figures this time, and the speaker listed panel connectors as a follow-on use case.

• A head-to-head with micro-VCSELs. The speaker himself called it a bake-off on reliability, temperature tolerance and power efficiency. The >200°C tolerance drew a pointed remark from the floor that few people need 200°C; the speaker replied that even at 125°C temperature tolerance is not the problem, effectively demoting temperature from selling point to entry ticket.

• If the SerDes stays, the value is discounted. A native wide interface requires XPU, switch or HBM makers to change their chip designs, which Avicena cannot decide alone.

• The capacity claim needs verification. The speaker said the display industry already built ample capacity for a large company that later chose not to go this way, but named no supplier and did not explain whether high-speed µLEDs can reuse display lines directly.

7. What It Means for Taiwan's Supply Chain

• TSMC is the only Taiwanese partner named in the slides or the talk. Avicena's PD array is optimized from TSMC's CMOS image sensor process, and the whole solution is pitched as silicon-based. If µLED reaches volume, the receive side becomes a new application for mature CMOS processes rather than new compound semiconductor capacity.

• Scale-in hinges on the HBM base die. Avicena's scale-in architecture puts µLED I/O on the HBM base die, and all three HBM makers are its investors. With HBM4-generation base dies moving to foundry logic processes, whether µLED I/O can be integrated into the base die becomes a joint design question for memory makers and foundries, not just for optics companies.

• Display microLED capacity is a possible spillover, but there is no evidence yet. The speaker only said display capacity is ample and named no supplier; whether Taiwan's microLED display makers can participate depends on whether high-speed µLED epitaxy and mass-transfer specs can be shared with displays, and it is too early to infer.

8. Conclusion

The real message of this talk: whether µLED interconnect wins depends on whether the SerDes gets removed, not on how fast µLEDs can run. Avicena's <1 pJ/bit, near-zero latency and >10 Tbps/mm² all rest on native wide interfaces in the XPU and HBM; the 1.6T to 6.4T optical engines and AOCs coming next year are transitional products that buy a qualification ticket, and the host SerDes will eat most of their efficiency advantage.

The timing runs on two tracks. On scale-up cables, Avicena must fight both copper and micro-VCSELs within 10 m; on scale-in, HBM is already a wide-and-slow interface and all three memory makers are investors, making it the only battlefield where µLED does not first have to compromise with the SerDes. Over the next 12 to 18 months, watch for reliability data, the optical engines' electrical interface spec, and the first chip design that publicly adopts µLED I/O.

µLED is not here to replace the laser but the SerDes on the die edge; if the SerDes stays, µLED is just a lighter AOC.

This article is for technology and industry trend analysis only and does not constitute investment advice.