ECOC 2026 | Microsoft Writes the Spec Sheet for Optical I/O: <1 pJ/bit, >10 Tbps/mm, ~10 m, <<1 FIT, <10 ns
This was the most "customer-side" talk of all of ECOC 2026. The Microsoft speaker opened by calling it a research presentation, full of assumptions and risk — then did something no one else did: he wrote down, line by line, the specs optical I/O must hit to replace in-rack copper interconnect. Power below 1 pJ/bit, bandwidth density above 10 Tbps/mm, reach of about 10 meters, reliability far below 1 FIT, latency under 10 ns. Taken together, these five numbers amount to a declaration that today's fast-and-narrow path cannot get there — because even if the optics consumed zero power, the SerDes alone already exceeds 1 pJ/bit. So the bet is on wide-and-slow + microLED. And the sharpest line of the whole talk was on a slide: "The package is no longer the unit of design, assembly and failure — the die is."
1. One chart, three technology tiers, an order of magnitude apart
The talk opened with a calibration chart: the x-axis is maximum reach (0.001 m to beyond 100 m), the y-axis a combined figure of merit — bandwidth density × energy efficiency, in (Gbps/mm)/(pJ/bit); higher is better.
The three technologies used in data centers today line up along a diagonal on this chart:
Wide-and-slow parallel copper traces: typical use die-to-die (D2D), GPU to HBM; figure of merit ~100,000; max reach ~0.001 m
Narrow-and-fast copper cables: typical use NVLINK scale-up; figure of merit ~200; max reach ~1 m
Narrow-and-fast optical cables: typical use InfiniBand/Ethernet scale-out; figure of merit ~10; max reach ~50–100 m
Each tier down loses roughly an order of magnitude in figure of merit. That is not coincidence but physics — to go farther you must serialize parallel lanes, push up the data rate, and add equalization and DSP, and every step eats into bandwidth density and energy efficiency.
The speaker nailed this down with a public comparison: look at the Vera Rubin specs — from HBM bandwidth to scale-up to scale-out, each tier shrinks by roughly 10x. And this is not unique to NVIDIA; other GPU vendors follow the same architectural philosophy.
2. Four walls — and today's fixes all pile on complexity
He then broke "interconnect is the bottleneck" into four levels, giving the industry's current fix for each — and every one of those fixes trades complexity for time.
Wall one: compute. Hopper (H100) is a single die; Blackwell is two dies; Vera Rubin Ultra is expected to be four dies; push further and you reach Cerebras' wafer scale. The verdict on the slide was blunt: high packaging complexity and cost, and fundamentally limited by wafer size. The reason: model compute demand grows 10x per year, while Moore's Law delivers only about 2–3x per generation.
Wall two: memory. HBM has to sit right next to the GPU, and there is no room left beside it — the speaker likened it to "Manhattan: the only way is up." Hence HBM3 (8-high) → HBM4 (12-high) → HBM5 (16-high) → HBM 3D-stacked on the XPU. But the more layers, the thinner each must be — and the base die at the bottom is the heat source, so pulling heat out through a dozen-plus layers is very hard. More critically, bit density: HBM holds roughly 4x fewer bits than standard DRAM, because space must be set aside for the TSVs that carry signals through.
Wall three: scale-up. Copper cables deliver very high bandwidth, but only reach about one meter. So the only option is to cram GPUs into a single rack. Today Azure production runs 120 kW per rack — and in the real deployment photo on the slide, the actual GPU rack takes up only a small slice; everything else is cooling infrastructure. The next generation is expected to exceed 0.5 MW. The speaker's analogy was vivid: a rack is the size of a parking space — two meters by one. Put half a megawatt in there.
Wall four: scale-out. Across racks there is 10x oversubscription, with 800G optics per GPU. And this is where software complexity comes from: today a rack holds 72 GPUs; if a model needs only 64, 8 are wasted; if it needs 80, those 8 land in another high-bandwidth domain with no bandwidth in between. Tensor parallelism, expert parallelism, pipeline parallelism, data parallelism — these tricks exist entirely to work around interconnect limits.
And the workloads themselves are heterogeneous. Inference has at least three phases: prefill (time to first token), decode attention and decode expert — and agentic workloads now add a fourth, "midfill." Each needs a different compute-to-memory ratio — NVIDIA already sells two kinds of hardware optimized for different scenarios.
3. If optics were cheap enough, the whole architecture could be rewritten
This is the pivot of the talk, and the speaker's framing is interesting — he defines "cheap" broadly: low power, low cost, low latency, high reliability.
Suppose such an optical interconnect really existed — what would happen?
Package level: Today it is "one big package with everything stuffed in" — dies, HBM, all crammed onto the same silicon interposer. Tomorrow it could be many small packages, one die per package, each with its own optical port, with compute packages and memory packages linked by an optical fabric.
The conclusion on that slide is, in my view, the single line from this talk most worth remembering:
The package is no longer the unit of design, assembly and failure. The die is.
Memory level: If memory no longer has to sit next to the GPU, there is no need for HBM. You can use DRAM — cheap, high-bandwidth, easy to cool. Even LPDDR, since density is no longer a concern.
Rack level: There is no need to cram everything into one rack. The rack shrinks to a convenient unit of deployment, decoupled from the compute unit.
Software level: This is the part with the most commercial significance. Today ratios are fixed at design time: if a workload is memory-bound and needs 1 part compute to 6 parts memory while the hardware has a fixed ratio, you end up with compute dies that were bought and powered on, yet sit idle. The example on the slide spelled it out — two compute dies and five memory dies stranded. With an optical fabric, the ratio can be set per workload at runtime; nothing is stranded, and spare resources simply wait for the next job.
The slide's subheading condensed it into one line: from design-time decisions to runtime decisions.
4. The spec sheet: five numbers, each one hard
This is the most valuable slide of the talk, because it turns "how good must optical interconnect be" from adjectives into numbers. The speaker stressed it is not a product requirement or an official position, but his own judgment. Still, it is a table you can hold a datasheet up against:
Power: target < 1 pJ/bit (W/Tbps)
Bandwidth density: target > 10 Tbps/mm
Reach: target ~10 m
Reliability: target << 1 FIT
Latency: target < 10 ns
Each number comes with its own reasoning, and latency is the one most worth a look.
The speaker said: for networking, paying an extra 100 ns for DSP doesn't matter. But for memory access, local memory latency is 80 ns — paying another 50–100 ns for an extra modulator, DSP or FEC is unacceptable, because it more than doubles memory latency.
This one line rules out many existing approaches. Any optical interconnect that needs DSP cannot serve memory.
The reasoning behind the reliability target is just as direct: because it is co-packaged, any single failure affects the entire system.
5. Why wide-and-slow: SerDes is the ceiling
Next came an energy breakdown splitting optical I/O energy per bit into five pieces — SerDes, D2D, Analog, Light source and Other — shown as bars across four architecture generations.
Pluggable modules: the tallest bar, and SerDes is the elephant in the room — visually more than half of it.
CPO: much shorter. This is exactly what the industry is doing now — removing part of the SerDes (LRO/linear drive). A lot has already been cut.
But then the speaker delivered the most important judgment of the talk:
Even if the optics consumed zero power, the big SerDes block remains. So any fast-and-narrow approach will struggle to get below 1 pJ/bit.
That is why they bet on wide-and-slow. With a very large number of lanes at a low rate, the SerDes can be removed outright (replaced by D2D), and the drivers and TIAs run at very low rates, so equalization is simple enough that CTLE-level suffices. The light source can also be swapped for something cheaper — such as microLED.
The third bar, "Wide-and-slow," is therefore just a stub: mostly D2D and analog, plus a little light source.
And the fourth is "3D Stacking" — microLED/PD arrays stacked directly on top of the compute die, eliminating even D2D, because the distance is so short there is "effectively no trace." The slide reads: < 1 pJ/bit ?
That question mark is honest. In the top-right corner of every slide the speaker put a risk gauge: from "low to medium" for CPO, to "medium to high" for wide-and-slow, to "high to very high" for 3D stacking. He put it plainly: "I won't lie to you — there are a lot of unknowns here."
6. Wide-and-slow's three other advantages — none of them about power
The speaker made a point of saying "don't talk only about power," and the case for wide-and-slow on three other dimensions is actually more interesting.
Reliability: with so many lanes, the marginal cost of adding a few more is essentially zero. So you can play the game computer science has played in storage for decades — redundancy. Provision 1.2x or 1.3x the lanes and you can tolerate failures. Set against the "<< 1 FIT" target above, that amounts to saying: reliability comes not from making each component ultra-reliable, but from the architecture.
Bandwidth density: microLED-type devices are top-emitting. That means linear shoreline density can be converted into areal density — and the pitch can be made extremely small, packing a great many emitters into the same space. Once you go to 3D stacking, you bypass the shoreline limit entirely and can use the full area of the XPU.
Latency: the link becomes very simple. It goes from a system "with FEC, DSP and equalizers" to "just analog drivers and TIAs, maybe a bit of CTLE." So latency is a few nanoseconds at most.
As for the speed of microLED itself, an audience member asked directly. The speaker's answer: currently about 2 Gb/s. But he immediately reframed the question —
In conventional technology, each generation you just double the rate. Here you can play many games: you can raise the rate, but you can also shrink the pitch and make the array larger. Shrink the pitch 5x and you get 25x more lanes.
And from an electronics standpoint, the higher the rate, the more complex the circuit. So his conclusion: what matters is the end-to-end pJ/bit, bandwidth density and reliability of the whole N-lane system, not the per-lane rate.
This "fast-and-narrow vs. wide-and-slow" debate also filled a three-hour ECOC 2026 workshop without consensus; our write-up: ECOC2026 | Fast-narrow vs. slow-wide argued for three hours and no one defined "slow" first: the real dividing line is 448G.
7. Cross-stack co-design: microLED is just one piece of the puzzle
The speaker kept stressing one point: "People keep asking me about microLED, this technology, that technology. But to me, microLED is only one small piece of the puzzle."
The diagram he showed breaks an optical link, left to right, into eight stages:
Transmit side: transmitter driver → microLED array → lens array → connector
Fiber
Receive side: connector → lens array → PD array → TIA/front end
And the subtitle reads: cross-stack co-design is the key to unlocking the full benefit.
He singled out two of those stages for comment, both worth Taiwanese suppliers' attention:
The photodetector (PD) is badly underrated. In his words: "For some reason I feel photodetectors don't get enough attention. To me, the more sensitive and better the detector, the easier life is for the TIA. If we can squeeze out a bit more there, we need to squeeze less elsewhere."
The TIA side also has plenty of room to play — not just lower power, but also tighter pitch.
And everything constrains everything else: "Whether certain fiber solutions work depends on the packaging; whether certain packaging solutions are feasible depends on component pitch and layout. So you can't focus on one piece and assume someone else will handle the rest."
Packaging is where everything converges — if you want high density and high reliability, packaging is the key.
His closing line applies to the entire optical communications industry: "When we talk about pluggable modules, saving 0.2 or 0.3 pJ/bit doesn't matter. But if you're aiming for 1 pJ/bit, every bit counts."
8. The validation deadlock: the real pain point of this talk
In the final section, the speaker raised a problem I think the whole industry should take seriously — the slide even gave it a title: Breaking the validation deadlock.
The deadlock is a perfect loop:
Volume adoption requires validation at scale. Validation at scale requires real deployments.
And real deployments require volume adoption.
He was candid: "I've talked to many startups and many large companies. Everyone has a favorite technology, but they're all still in the lab. It's hard to break out of this loop, so we tend to stick with what we know — which is good in a way, but on the other hand I think it stifles innovation."
Microsoft's answer is a staged deployment path:
Initial deployment: a controlled use case with limited integration risk
Field evidence and supply-chain build-out: reliability, serviceability, operational experience
Broader adoption: higher-value architectures after further validation
Their own roadmap: AOC PoC (March 2026, the first microLED pluggable proof of concept, announced at OFC) → connectorized pluggable module (in progress) → optical I/O (next).
He was honest about it: pluggables may not be microLED's ultimate market, but they are compelling enough to generate volume — and volume brings validation, which is what lets you move on to more advanced architectures.
And one remark was aimed squarely at the supply chain: "Some of the technologies we use weren't designed for this space — they were designed for consumer markets. Adapting them isn't easy. Part of the resistance we've hit is that the supply chain isn't ready. So we collectively need to help them scale — give them demand, or at least give them a standard to measure against."
9. Conclusion
Placed in the context of ECOC 2026, this talk occupies a special position: Corning on FAU reliability, the EBO MSA on connector contamination, Lumentum on laser power thresholds, Huawei on switch shoreline density — all of those are about perfecting one link within the existing architecture. Microsoft's talk asks: "If optics were cheap enough, why would we keep this architecture at all?"
For Taiwan's supply chain, three concrete takeaways:
First, copy down that spec sheet — especially the <10 ns line. Because it is an exclusionary spec — not "lower is better" but need DSP and you're out. That draws a very clean line for judging which application tier your solution can enter: if you can do <10 ns, you can talk memory and scale-up; if not, you stay in scale-out. And >10 Tbps/mm is more than 30x Huawei's 0.3 T/mm target for its 1024-lane switch — it is no longer the same application.
Second, microLED's 2 Gb/s should be read as neither bad news nor good news. The speaker's framing is clear: per-lane rate doesn't matter; what matters is the end-to-end pJ/bit and bandwidth density of the N-lane system. For Taiwanese suppliers, the real opportunity is not "making faster microLEDs" but pitch, lens arrays, connectors and packaging — because "shrink the pitch 5x, get 25x more lanes" depends on precision structural parts and packaging capability, not epitaxy.
Third, and most practical — he said publicly that "the supply chain isn't ready." Coming from a hyperscaler, that means: they are looking for partners willing to commit capacity to this path, and they know they can't offer order volume yet. This is a classic early-bet window: those who get in bear the cost of the validation deadlock, but also gain a voice in setting the spec. The question for Taiwanese suppliers is not "will microLED succeed" but "how much does it cost to convert consumer microLED lines to data center use, and is anyone willing to share that cost".
Verdict: The most valuable thing in this talk is not microLED but that spec sheet and the line "the package is no longer the unit of design — the die is." The former turns "how good must optical interconnect be" from adjectives into acceptance-testable numbers; the latter explains why it is worth the risk — if optics are cheap enough, HBM can revert to DRAM, the rack can be just a deployment unit, and resource ratios can be decided at runtime. This is not about shaving a few percent of power; it is about reclaiming design freedom for the entire AI infrastructure.
This article is for technology and industry trend analysis only and does not constitute investment advice.
Related reading
After copper can't keep up with AI: seven paths to scale-up optical interconnect, and two ways to live with the walls each one hits: a full breakdown of the fast-and-narrow vs. wide-and-slow yardstick, and how the seven approaches coexist in layers
ECOC2026 | Data centers need billions of lasers, but the bottleneck is the 5 minutes it takes to "attach" them: the light-source workshop at the same ECOC — the other side of the packaging and alignment capacity bottleneck
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