Technical Analysis | NVIDIA Lays Its Entire "Optics-in-Interposer" Stack on the Table: From an ECOC Concept to ISSCC Production-Grade Silicon

Over the past three years, NVIDIA has disclosed an optical interconnect technology piece by piece across four top-tier conferences (ECOC 2023, ISSCC 2026, OFC 2026, ECTC 2026) plus a microring patent. Line them up and it becomes clear these are not five isolated studies, but one vertically integrated weapon deliberately split into four layers and completed layer by layer: link and clocking, platform and packaging, light source, and a roadmap not yet in production. This article merges the five publications into a single technology map.

From the 2-wavelength proof of concept at ECOC 2023, to production-grade 256 Gb/s 3D-stacked optical I/O at ISSCC/OFC 2026, the ECTC 2026 laser source, and on to the bidirectional microring patent. Source: Simple Tech Trend

1. One Team, Three Years, Five Publications

The author lists of these five publications overlap heavily — Mehta, Rekhi, Nedovic, Song, Lee, Gray, all from NVIDIA/NVResearch, with Lumentum also on the light-source paper. This is not academia piecing together separate puzzle fragments; it is the same team disclosing different facets of the same system at different conferences:

• ECOC 2023: a 2-wavelength, 20 Gb/s microring clock-forwarded link (GF 45SPCLO monolithic) — where the whole story begins.

• ISSCC 2026 (23.1): 32 Gb/s/λ, 256 Gb/s/fiber half-rate band-pass-filtered clock forwarding, with a 3D-stacked 7nm EIC / 65nm PIC.

• OFC 2026 (M4B.2): the platform and packaging view of the same 256 Gb/s optical I/O.

• ECTC 2026: an 8-channel DWDM CW-DFB laser array and ELSFP, answering "where does the light come from."

• US 2024/0385381 A1: a bidirectional microring optical link architecture — the next step on the roadmap.

When a company is willing to lay out such a complete line across four top-tier conferences plus a patent at the same time, it has long left the exploration phase and entered the show-your-hand phase.

2. Copper Can No Longer Hold the Scale-Up Segment

For scale-up interconnect between GPUs (the NVLink segment), copper has hit its physical ceiling. NVLink went from 160 GB/s on Pascal (2016) to 1,800 GB/s on Blackwell (2024), and Rubin (2026) is estimated to reach 3,600 GB/s. Every doubling pushes copper interconnect closer to four walls: exponentially growing channel loss, power density hitting its ceiling, accumulating retimer latency, and running out of routing space at the rack boundary.

"Figure 2: The Four Walls of Copper Interconnect". Source: Simple Tech Trend

Original figure "Figure 3: Microring Clock-Forwarded DWDM Link (8 Data + 1 Clock)". Source: Simple Tech Trend

──────────────────────────────

That concludes the key takeaways of this article.

STT's full analysis — how the four layers of this stack interlock, why band-pass-filtered clock forwarding is the most original move, how 3D stacking squeezes out parasitics, how two humble laser numbers determine the energy of the entire link, what the bidirectional microring patent reveals about the next step, and what shape this stack bends the supply chain into (Coherent, Lumentum, FOCI, TSMC COUPE) — who gets on board and who gets sidelined — is covered in the paid section (including a figure-by-figure breakdown of 10 original technical figures).

👉 Subscribe to the STT paid section — read the full analysis on vocus (in Chinese)

──────────────────────────────

Related Reading

• ECTC 2026 | NVIDIA | Light Should Not Be Forced into Electrons and Back into Light

• NVIDIA Buys Into Optics: When Optical Communications Turns from Growth Stock to Index Heavyweight (W26)