To Understand Slow-and-Wide Optical Interconnects, First Understand SerDes and Die-to-Die

1. Why every slow-and-wide conversation ends up at SerDes

More and more people have been asking about slow-and-wide optical interconnects this year, from microLED and microVCSEL to the multi-wavelength NRZ of OCI MSA. The questions are remarkably consistent: "A microLED only runs a few Gbps, how can it compete with a 200G laser?" "Didn't silicon photonics already kill VCSELs?" "Isn't NRZ last-generation technology?"

All three questions point the wrong way. In our microLED interconnect series, and in ECOC and OCP breakdowns such as It's Not Physics Killing Slow-and-Wide, It's 60,000 Fibers, we keep seeing the same thing: whether an optical link pays off is often decided not by the optics, but by which language the electrical chip next to it speaks.

There are two such languages. One is SerDes, the other is Die-to-Die (D2D). Plenty has been written defining each, but few explain them side by side: they are not two specifications, but two opposite philosophies of moving bandwidth. Once you see those two philosophies, most of the debate around slow-and-wide news turns out to have been settled long ago.

This is a free primer with one goal: the next time you see an optical interconnect headline quoting "X Tbps, Y pJ/bit, Z meters", you will know which three questions to ask.

2. It looks like a light-source contest, but it is really about how you split bandwidth

First, clear up a misconception. Optical interconnect comparisons are often reduced to component battles: laser vs LED, silicon photonics vs VCSEL. But the component is a consequence. Upstream there is a more fundamental choice:

Total bandwidth = per-lane rate × number of lanes

To move 1.6 Tbps you can run 8 lanes at 200G, 64 lanes at 25G, or even 800 lanes at 2G. On paper they are identical, but the costs are completely different in kind:

• A few very fast lanes: few pins and few wires, but every lane needs complex circuitry to fight high-frequency loss. The money goes into the IC.

• Many slow lanes: each lane's circuitry is so simple it barely needs any processing, but you need a huge number of wires and a package that can route them neatly. The money goes into the channels.

The first is the world of SerDes; the second is the world of Die-to-Die. That microLED only runs a few Gbps and DWDM only runs NRZ is not a weakness: they are destined to sit on the second side. The real question is whether the chip they connect to is willing to move over.

3. SerDes: merging eight local lanes into one highway

3.1 Why SerDes exists

A chip has a limited number of pins. To move 102.4 Tbps through a switch chip at 1 Gbps per pin, you would need more than 100,000 pins, which simply cannot be packaged. SerDes (Serializer/Deserializer) solves this: on the transmit side it queues a row of slow parallel data into a single high-speed serial signal, and on the receive side it splits that back into parallel data.

Think of it as a highway on-ramp: traffic from eight slow city lanes merges into one 300 km/h express lane, and fans back out into city streets at the next town. Pins are saved, but that one lane has to be extremely reliable.

▲ How SerDes works. The transmitter serializes parallel data, then drives it through a lossy channel with feed-forward equalization (FFE); the receiver uses an analog front end, ADC and DSP to recover the attenuated signal, and clock-data recovery (CDR) extracts the clock and deserializes. The higher the rate, the more the receiver has to do (Image source: Simple Tech Trend original; data from Wikipedia, Synopsys, Cadence 224G SerDes IP materials, IEEE JSSC 2023)

3.2 Example: 512 lanes of 200G on one chip

The clearest example is Broadcom's Tomahawk 6, which began shipping in June 2025. It is the first single-chip 102.4 Tbps Ethernet switch, and its I/O comes in two configurations: 512 lanes of 200G PAM4 SerDes, or 1,024 lanes of 100G SerDes. Broadcom specifically highlights that its 200G SerDes can drive long-reach passive copper, one of the chip's key selling points.

In other words, the edge of today's AI networking chip is almost entirely occupied by SerDes. GPUs are the same: every external NVLink link is, at its core, a set of high-speed SerDes.

3.3 The cost: every doubling of speed makes the receiver work much harder

The trouble with SerDes is that copper loss grows non-linearly with frequency. Double the rate, the Nyquist frequency doubles, and channel loss soars. Engineers respond by stacking circuit after circuit:

• Feed-forward equalization (FFE) at the transmitter to pre-distort the signal

• Continuous-time linear equalization (CTLE) and a high-speed ADC at the receiver to digitize the analog signal

• A DSP with dozens of taps of digital equalization and decision-feedback equalization (DFE), plus maximum-likelihood sequence detection (MLSD) at 224G

• Finally, forward error correction (FEC) as the safety net

All of this costs money, area and power. Academic 224G SerDes figures give a sense of scale: a 5 nm 224G PAM4 receiver consumes about 1.41 pJ/bit in its analog section alone; a 3 nm 224G long-reach transceiver totals about 3 pJ/bit in analog, occupying 0.5 mm² per lane. That is before counting the digital power of the DSP. Alphawave offers an intuitive comparison: with the same architecture, moving from 112G to 224G shrinks usable reach from about one foot to about one inch, which is why DSP became mandatory.

This figure shows the DSP chain of a 112G-and-beyond PAM4 SerDes receiver: after ADC digitization come FFE, DFE and clock recovery, then MLSD and FEC. The four bullets above are the boxes in this diagram, and every box burns power.

▲ PAM4 DSP for 112G and beyond: the digital signal processing chain in a high-speed SerDes receiver (Image source: Synopsys / Semiconductor Engineering)

Reach shrinks in step. Marvell gave a set of numbers at ECOC 2026: going from 100G to 200G per lane cuts passive copper reach from 5 m to 2.5 m; at 400G only 1.25 m remains. The SerDes roadmap is a roadmap of running faster, reaching shorter and burning more power.

This figure shows Marvell's ECOC 2026 projection: each doubling of lane rate halves passive copper reach. The faster SerDes gets, the smaller the range copper can cover directly, and that is exactly where optics has to take over.

▲ Marvell: each doubling of lane rate halves passive copper reach, about 2.5 m at 200G and only 1.25 m at 400G (Image source: Marvell | ECOC 2026 Symposium presentation, photographed on site by Simple Tech Trend)

4. Die-to-Die: a thousand-lane surface road inside the package

4.1 Why D2D exists

The SerDes world assumes wires are expensive, so you pull few of them and run each fast. Inside a package, that assumption no longer holds.

The reason is that AI chips have hit the reticle limit. The largest die a single exposure can print is about 858 mm², and NVIDIA's previous-generation GH100 already reached 814 mm², leaving almost no room to grow. The answer is to split one large chip into two or more dies in the same package, connected through a silicon interposer or silicon bridge.

Wiring on a silicon interposer is made with semiconductor processes at micron-scale pitch. Here wires are not expensive at all; you can run tens of thousands of them at once. Since wires are cheap, there is no need to run each one fast, so D2D interfaces take the opposite path: massive parallelism, low speed per lane, NRZ modulation, almost no equalization and no DSP at all.

In road terms: SerDes is an intercity highway, while D2D is a thousand-lane surface road between two buildings on the same campus. Every lane drives slowly, but there are countless lanes and the buildings are only a street apart.

▲ Two ways to move 1.6 Tbps. On the left, SerDes uses 8 lanes of 200G PAM4, each needing FFE, CTLE, ADC, DSP and FEC; on the right, D2D uses 64 lanes of 25G NRZ with only a simple driver and receiver per lane, but it requires a silicon interposer for dense wiring and reaches only millimeters (Image source: Simple Tech Trend original; data from UCIe Consortium, OCP BoW specification, IEEE JSSC 2023)

4.2 Examples: two cases that turned two dies into one chip

Apple UltraFusion (M1 Ultra, 2022): Apple placed two M1 Max dies side by side and connected more than 10,000 signals through a silicon interposer, delivering 2.5 TB/s of die-to-die bandwidth so the operating system sees the two dies as one chip. It was the first large-scale demonstration of D2D in a consumer product.

This figure shows the structure of M1 Ultra: two M1 Max dies, top and bottom, with the narrow strip between them being UltraFusion. All 10,000 signals are squeezed along that stretch of die edge, the most intuitive picture of what "die-edge length" means.

▲ M1 Ultra is built from two M1 Max dies joined by the UltraFusion silicon interposer carrying more than 10,000 signals (Image source: Apple, via All About Circuits)

NVIDIA Blackwell NV-HBI (B200, 2024): Blackwell builds one GPU from two near-reticle-limit dies (about 104 billion transistors each), joined by NV-HBI at 10 TB/s, with latency low enough that software sees a single GPU. Compare that with Blackwell's external NVLink 5 at 1.8 TB/s per GPU: in-package D2D bandwidth is more than five times the off-package SerDes bandwidth. That is no coincidence; it is D2D's structural advantage.

This figure shows Blackwell's dual-die package: two dies side by side on CoWoS-L, with NV-HBI between them delivering 10 TB/s. Compare it with the external NVLink bandwidth on the same slide to feel the gap between inside and outside the package.

▲ NVIDIA Blackwell uses NV-HBI to provide 10 TB/s between its two dies, so software sees a single GPU (Image source: NVIDIA | Hot Chips 2024 presentation, via ServeTheHome)

4.3 Standardization: UCIe and BoW

Early D2D links were proprietary: Apple had its own, NVIDIA had its own, and dies could not be mixed and matched. From 2022 the industry began standardizing, with two main specifications:

• UCIe (Universal Chiplet Interconnect Express): developed by Intel, AMD, TSMC and others, and currently the mainstream choice. UCIe 3.0, released in August 2025, raises the per-lane rate from 32 GT/s to 48 and 64 GT/s while keeping the energy-efficiency target at 0.5 to 0.75 pJ/bit. On advanced packaging (UCIe-A), one module has 64 lanes at 64 Gbps each, about 4 Tbps in total.

• BoW (Bunch of Wires): a specification under the Open Compute Project, named exactly for what it is. It is designed to work on low-cost organic substrates as well as advanced packaging, so smaller chip companies can also play the chiplet game.

Both specifications share one term worth remembering: beachfront (or shoreline), the length of the die edge. D2D competes not on how fast one lane runs, but on how much bandwidth each millimeter of die edge can deliver (Tbps/mm) and how much energy each bit costs (pJ/bit). These are exactly the metrics slow-and-wide optical interconnects use in their marketing.

This figure shows the key UCIe 3.0 metrics: within D2D, how standard packaging (UCIe-S) and advanced packaging (UCIe-A) differ in module width, bandwidth density (GB/s/mm) and pJ/bit. Advanced packaging has denser wiring, so the same die edge carries more bandwidth.

▲ UCIe 3.0 key metrics: 48/64 GT/s data rates, bandwidth density and energy-efficiency targets by package type (Image source: UCIe Consortium, via Semiconductor Engineering)

This figure shows the bump layout of a UCIe-A x64 module at the die edge: 64 data lanes plus clock, power and ground, escaping in 10 rows. It draws the physical cost of slow-and-wide: being wide means occupying this much die edge.

▲ UCIe-Ax64 10-row PHY bump map and signal escape routing (Image source: UCIe Consortium, via Synopsys)

5. SerDes vs D2D in one table

Item	SerDes (fast and narrow)	Die-to-Die (slow and wide)
Per-lane rate	100G to 200G, heading to 400G	A few Gbps to 64 Gbps
Lane count	Few (4 to 8 per port)	Many (tens to tens of thousands)
Modulation	PAM4	NRZ
Reach	Centimeters to meters (copper), kilometers with optical modules	Millimeters to a few centimeters
Main power consumers	Equalization, ADC, DSP, FEC	The driver and receiver themselves
Energy efficiency	Several pJ/bit and up (excluding optics)	Below 1 pJ/bit
Bottleneck	Higher frequency means shorter reach and higher power	Short reach; requires advanced packaging
Examples	Broadcom Tomahawk 6, external NVLink links	Apple UltraFusion, NVIDIA NV-HBI, UCIe, BoW

One line to remember: SerDes solves "not enough pins"; D2D solves "the chip is too big". The former spends power on circuitry to reach far; the latter saves power because it does not need to.

6. Back to slow-and-wide: every approach is doing the same thing, stretching D2D between racks

Now we can answer the opening questions. Whether it is microLED, VCSEL arrays or multi-wavelength DWDM NRZ, none of them ever intended to compete with 200G lasers on per-lane rate. They all want the same thing: to take D2D's slow, wide, DSP-free philosophy and use light to stretch it from a few millimeters inside a package to 10 to 50 meters between racks.

The only difference is where the "wide" comes from. Slow-and-wide approaches can stack up lane count along two dimensions:

Where "wide" comes from	Per-lane rate	Representative approaches	Main challenges
Spatial parallelism: more emitters, more fiber cores	2–4 Gbps (microLED) / 25–50G NRZ (VCSEL)	Avicena, Microsoft MOSAIC, Coherent 2D VCSEL, Broadcom VCSEL NPO	Fiber count, multicore fiber and connectors, array yield
Wavelength parallelism: more wavelengths per fiber	32–100G NRZ	OCI MSA, NVIDIA DWDM, imec 3D optical I/O	Multi-wavelength light sources, channel spacing and thermal control, MUX/DEMUX

The physics of the two paths is completely different, but from the chip's point of view they are the same: both need a "many lanes, slow" electrical interface in front to feed them data. That is why they hit the same bottleneck (Section 7).

▲ Reach vs energy efficiency (log-log). D2D sits at millimeters and 0.5 to 0.75 pJ/bit; SerDes plus passive copper at meters and 3 to 6 pJ/bit; full 800G laser-based pluggable links at about 12 to 15 pJ/bit. In the slow-and-wide camp: Microsoft MOSAIC's complete microLED cable at about 3.9 to 6.6 pJ/bit, slow-and-wide VCSEL optics alone at about 1 to 1.5 pJ/bit, Avicena claiming below 1 pJ/bit for the optical segment, and imec 3D optical I/O targeting 0.25 to 0.5 pJ/bit. The green dashed box is the goal: 10 to 50 m reach at near-D2D efficiency. Any optics-only figure needs about 4 pJ/bit added if a reverse GearBox sits in front (Image source: Simple Tech Trend original; data from UCIe Consortium, Microsoft Research (MOSAIC, SIGCOMM 2025), Avicena press releases, ECOC 2026 speaker presentations; scopes differ, for order-of-magnitude comparison only)

6.1 Spatial parallelism I: microLED, the slowest and widest

US startup Avicena's LightBundle is the most direct example. It uses GaN microLED arrays as emitters, CMOS-compatible photodetector arrays as receivers, and multicore fiber bundles in between. From the start, Avicena positioned it as an optical extension of parallel chiplet interfaces (UCIe, OpenHBI, BoW), and at OFC 2024 said its first D2D implementation would be an 8 Tbps UCIe advanced-package interface, aiming to extend HBM-class links to 10 meters.

The numbers keep falling: at ECOC 2025 a single microLED driven at 0.25 mA ran 4 Gb/s at about 200 fJ/bit on the transmit side, with a raw BER below 1e-12 and no FEC; at SC25 the drive current dropped to 100 µA, or roughly 80 fJ/bit. Note this is a per-LED transmit-side figure, not the whole link. Section 8 comes back to this distinction. For details see our breakdown of Avicena's OCP 2026 talk.

Microsoft Research's MOSAIC won the Best Paper award at ACM SIGCOMM 2025, with "wide-and-slow" right in its title. The prototype has 100 channels at 2 Gbps each; at 2 Gbps per channel, 800G needs only a 20×20 microLED array under 1 mm². Microsoft claims reach up to 50 m (more than ten times copper), up to 68% lower power and reliability two orders of magnitude higher than current optical links, with a purely analog electrical back end and no DSP. According to Tom's Hardware, Microsoft has completed proofs of concept with suppliers including MediaTek and aims to commercialize with industry partners by late 2027.

▲ Microsoft MOSAIC's microLED slow-and-wide link prototype, replacing a few high-speed laser lanes with hundreds of low-speed lanes (Image source: Microsoft, via SDxCentral)

6.2 Spatial parallelism II: VCSEL arrays, turning multimode optics slow-and-wide

At 2 to 4 Gbps per lane, microLED is so slow that 1.6T needs hundreds of lanes; conventional VCSELs at 100G PAM4 are fast-and-narrow. VCSEL arrays (including smaller, denser microVCSELs) take the middle road: 25G to 50G NRZ per lane, no DSP, and a lane count that stays under control.

• Broadcom's 100G VCSEL 3.2T NPO runs at about 1.5 pJ/bit (cited by Corning at ECOC 2026), well below the 5 to 9 pJ/bit of silicon-photonics CPO/NPO.

• Coherent launched 2D VCSEL and PD arrays in September 2025, explicitly described as "slow and wide": 1.6T, 850 nm, 32×50G NRZ, with a 1060 nm back-emitting flip-chip version previewed for 2026.

• Lumentum presented "Slow and Wide 12.8T" with 1060 nm VCSELs at OCP 2026, moving the VCSEL battle from speed to thermals and reliability.

• AUO's keynote at SEMICON Taiwan framed heterogeneously integrated µLED and µVCSEL slow-and-wide optical engines as a data-center direction; Taiwan's iReach is working with Brillink on flip-chip micro-VCSEL arrays; and at OCP 2026 LightXcelerate showed micro-VCSEL arrays with multicore fiber, see our LightXcelerate OCP 2026 breakdown.

The shared challenge of spatial parallelism is fiber count. More lanes means more fiber cores, more connectors and tighter alignment yield, which is the theme of It's Not Physics Killing Slow-and-Wide, It's 60,000 Fibers.

This figure shows Coherent's 2D VCSEL array die: not a single row, but a full plane of emitters. Moving from 1D to 2D arrays is how spatial parallelism stacks up "wide".

▲ Coherent 2D VCSEL array: 1.6T, 850 nm, 32×50G NRZ, designed for slow-and-wide scale-up (Image source: Coherent, 2025-09-25)

6.3 Wavelength parallelism: DWDM NRZ, hiding "wide" inside one fiber

The other path adds no fibers; it packs more wavelengths into the same fiber. Each wavelength runs only NRZ, and total bandwidth is stacked up by wavelength count. It is still slow-and-wide, except "wide" has moved from space to spectrum.

• OCI MSA (Optical Compute Interconnect) was founded in March 2026 by Meta, Microsoft, OpenAI, AMD, Broadcom and NVIDIA. The Gen1 specification is 4 wavelengths × 50G NRZ, bidirectional, 200G per fiber, moving next to 100G NRZ and then growing by adding wavelengths.

• NVIDIA showed 8 wavelengths × 32G NRZ, 256G per fiber at 200 GHz spacing at ECOC 2026, with all channels locked and running error-free for 16 hours.

• imec's 3D optical I/O goes further: the XPU is hybrid-bonded on top of an optical interposer, running 32G/64G NRZ with no DSP and using 32 to 64 wavelengths for bandwidth, targeting 0.25 pJ/bit.

Wavelength parallelism solves fiber count but shifts the challenge to the light source: you need multi-wavelength, narrow-spacing, high-power lasers that can be mass-produced. We cover both paths in detail in ECOC 2026 Fast-and-Narrow vs Slow-and-Wide.

This figure shows Broadcom's view of the electrical interface: 200G PAM4 can still be driven linearly, 400G maybe, 800G unlikely. So OCI lets the optics grow on its own with NRZ, DWDM and bidirectional transmission, instead of chasing SerDes speeds.

▲ Broadcom: why OCI MSA is needed. The electrical interface is unlikely to stay linear at 800G, so OCI uses NRZ, DWDM and BiDi to let the optics scale on their own (Image source: Broadcom | ECOC 2026 Symposium presentation, photographed on site by Simple Tech Trend)

7. The key factor: which language the XPU edge speaks

By now slow-and-wide looks attractive: low power, long reach, no DSP. So why did Largan say at its earnings call that microLED entering CPO is "unlikely to happen"? Why is 200G silicon photonics still the volume workhorse at NVIDIA and Broadcom? Why do OCI's 400G and 800G timelines still carry question marks?

The answer lies at the boundary between Sections 3 and 4. Today's GPUs, ASICs and switch chips all speak SerDes at their edges. What comes out is 200G or 400G PAM4 high-speed signaling, not thousands of slow parallel D2D-style wires.

So any slow-and-wide optics connecting to today's XPU needs a translator in between: a reverse GearBox. It splits one 200G or 400G SerDes signal into 4, 8 or even 64 low-speed NRZ signals, then hands them to VCSELs, microLEDs or individual DWDM wavelengths. This applies equally to spatial and wavelength parallelism.

▲ Two ways to connect. Top, today: the XPU's 200G/400G PAM4 SerDes first passes through a reverse GearBox (about 4 pJ/bit) to split into low-speed lanes, feeding VCSEL arrays (about 1:4 to 1:8), microLED arrays (about 1:64) or multi-wavelength DWDM NRZ (about 1:4 to 1:8). Bottom, the future: the XPU exposes a UCIe-style wide parallel interface directly, a slow-and-wide optical chiplet attaches like another die, and the GearBox disappears (Image source: Simple Tech Trend original; data from Arista (ECOC 2026), Avicena (OFC 2024), OCI MSA, STT slow-and-wide optical interconnect series)

The problem is that this translator is expensive. Arista gave two figures at ECOC 2026: the optics of an 8×50G NRZ VCSEL link cost only about 1 pJ/bit, but the 8:1 reverse GearBox in front eats about 4 pJ/bit; the DWDM version with a 4:1 GearBox also costs about 4 pJ/bit. Most of the power the optics saves is eaten back by the GearBox, whether your "wide" is fibers or wavelengths. The higher the conversion ratio, the more complex the GearBox, and microLED's 1:64 is the extreme end. That is why, if customers do not change their ASICs, slow-and-wide's end-to-end efficiency can actually be worse than fast-and-narrow.

Conversely, if XPU vendors one day expose a native wide parallel interface at the die edge, essentially a UCIe-style D2D interface, slow-and-wide optical chiplets can attach directly like another die, the GearBox disappears, and the efficiency advantage is fully realized. Avicena making UCIe its first product interface, imec stacking optics directly beneath the XPU, and both AMD and NVIDIA appearing among OCI's founders are all bets on that day.

That is the conclusion of our ECOC 2026 Fast-and-Narrow vs Slow-and-Wide piece: slow-and-wide is not losing on optics, it is losing on timing; XPU I/O is not yet ready to be redesigned for it.

8. Next time you see slow-and-wide news, ask these three questions

Condensed into three questions, the ideas above can unpack almost any related headline, whether the protagonist is microLED, VCSEL or DWDM:

1. How fast is each lane, how many are there, and where does "wide" come from? 4 Gbps × 400 lanes, 50G × 32 lanes or 32G × 8 wavelengths is completely different from 200G × 8 lanes. The first three follow the D2D philosophy, the last one SerDes; and whether "wide" comes from fibers or wavelengths decides whether the bottleneck lands on fiber count or the light source.

2. Which segment does that pJ/bit figure measure? A single emitter's transmit side, the optical engine, the whole link, or including the GearBox? Avicena's 80 fJ/bit is transmit-side; MOSAIC's power covers both ends of the cable. The two cannot be compared directly.

3. Does the electrical end connect to SerDes or D2D? If it connects to today's 200G SerDes, add the GearBox's 4 pJ/bit back in; if it connects to a D2D interface like UCIe, ask: which XPU vendor has actually exposed that interface?

The third question matters most, and it is the one asked least.

This figure places the pJ/bit numbers disclosed by ECOC 2026 speakers on a single scale: from ZR coherent, pluggables and CPO all the way to VCSEL NPO and imec 3D optical I/O. Note that each number covers a different scope, which is exactly what the second question asks you to pin down first.

▲ pJ/bit figures disclosed by ECOC 2026 speakers, ranked; scopes differ, for order-of-magnitude comparison only (Image source: Simple Tech Trend original; data from Arista, NVIDIA, TeraHop, Corning and imec presentations)

Conclusion

SerDes and Die-to-Die are not two spec names but two opposite worldviews: one spends power on circuitry to reach far; the other saves power because it does not have to. For the past decade SerDes ruled outside the package and D2D ruled inside it, and the two never crossed.

The ambition of slow-and-wide optical interconnects is to break that boundary and extend D2D economics between racks. microLED, VCSEL arrays and DWDM NRZ are simply three ways to build "wide", and all have been shown physically feasible: around 100 fJ/bit on the transmit side, 256G per fiber, and prototype links running tens of meters. Their common bottleneck is not the light, but the electrical interface at the XPU edge.

So the most useful signal to track is not the next fJ/bit record, but this: which XPU vendor will be the first to publicly expose a native wide parallel optical I/O interface at the die edge. Until then, slow-and-wide is great technology; after that, it becomes a business.

References

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• Simple Tech Trend, "ECOC2026 | Fast-and-Narrow vs Slow-and-Wide" (OCI MSA, NVIDIA DWDM, imec 3DIO and Arista GearBox figures compiled from ECOC 2026 Symposium speaker presentations), https://www.simpletechtrend.com/post/ecoc-2026-scale-up-xpo-cpo-oci-serdes

Related reading

• ECOC2026 | Fast-and-Narrow vs Slow-and-Wide: scale-up optical interconnect is decided by the SerDes at the die edge: where Arista's 4 pJ/bit GearBox comes from, details on OCI MSA and DWDM, and both camps' volume timelines

• It's Not Physics Killing Slow-and-Wide, It's 60,000 Fibers: the network's shape before 2029 and who benefits: slow-and-wide's other bottleneck, fiber count

• 2026 OCP Global Summit | Avicena | µLED Interconnects for Scale-In and Scale-Up: how the microLED camp positions itself

• 2026 OCP Global Summit | Lumentum | Slow and Wide 12.8T VCSEL Solutions: the VCSEL camp's slow-and-wide roadmap