OCP Global Summit 2026 | LightXcelerate | Weipeng Zhang, Manchen Hu | High-Density Optical I/O Using Micro-VCSEL Arrays and Multicore Fiber

1. Why a startup is the one talking about slow-and-wide

LightXcelerate was founded only in early 2025. Its talk ran in the Future Technologies Symposium during the OCP Global Summit (October 14), presented by CTO Weipeng Zhang. The opening matched every other optics speaker: AI performance stands on three legs, compute, memory and interconnect, and while the first two have been scaled hard, interconnect is now the one holding things back.

The more interesting part was the funding table on slide 3: since late 2025, strategic commitments in optics have exceeded $15 billion.

Deal	Amount	Nature
NVIDIA optics ecosystem investments (Lumentum, Coherent, Marvell, $2B each)	$6B	Announced March 2026
Marvell acquires Celestial AI	$3.25B	Completed February 2026
Meta–Corning fiber connectivity supply agreement	Up to $6B	Multiyear supply contract, not equity

The speaker's conclusion: "the question is no longer whether we need optics, but which optics." LightXcelerate's answer is directly modulated micro-VCSELs: the laser is inside the device, there is no external light source and no thermal tuning to stabilize wavelength, and each VCSEL runs at the native lane rate, so no gearbox is needed.

2. Breaking down the architecture: the optical engine as a 2.5D chiplet

LightXcelerate places its optical engine next to the XPU on the same substrate or interposer, connected to the XPU through a silicon bridge or silicon interposer. Four design points:

• Passive fiber alignment: pins on the fiber array unit (FAU) drop straight into a socket on the package lid

• Backside optics: backside-emitting (BSE) VCSELs and backside-illuminated (BSI) photodetectors are flip-chipped face-down, so light passes through the substrate straight toward the fiber

• EIC directly underneath: the driver and TIA sit right below the optical dies, separated only by micron-scale copper pillars

• Thermal: dummy silicon plus TIM carry heat into the lid

▲ LightXcelerate's optical engine architecture: the optical engine shares a substrate with the XPU, BSE VCSELs and PDs are flip-chipped onto the EIC, and the fiber array is passively aligned with locating pins (Image source: LightXcelerate | 2026 OCP Global Summit presentation)

The speaker also noted that the architecture is not limited to CPO. With new MSAs appearing at OCP one after another, the current plan is to complete all the building blocks, deliver the micro-VCSEL first in a module form factor, and later extend to other packaging forms (the transcript is auto-generated, so the exact form-factor names cannot be confirmed). For a startup, entering through modules before co-packaging is the more pragmatic sequence.

The first product block is LightX-1:

Metric	Value
Lanes	57 Tx + 57 Rx (three 19-channel subarrays, per-channel addressable)
Die size	1.5 × 0.6 mm
Per-lane rate	32 Gb/s NRZ, roadmap to 64G, then 100G and 200G
Bandwidth per engine	3.2 Tb/s
Full-link energy	< 1.5 pJ/bit
Reach	50 m

STT math: 57 × 32 Gb/s = 1.82 Tb/s per direction, or about 3.65 Tb/s for Tx plus Rx, which is more than the slide's 3.2 Tb/s. The speaker said "over 3 Tb/s total bidirectional," so 3.2 Tb/s should be a bidirectional total, but the slides do not explain the gap between 57 lanes and 3.2 Tb/s. One possibility is 50 lanes carrying data (50 × 32G × 2 = 3.2 Tb/s) with the other 7 used as spares or for other purposes; this is STT speculation pending confirmation from the company. On the 0.9 mm² VCSEL die, that is roughly 2 Tb/s/mm² per direction, or about 4 Tb/s/mm² at 64G.

3. The real trick: VCSEL pattern = fiber-core pattern

As we wrote in It wasn't physics that killed slow-and-wide, it was 60,000 fibers (in Chinese) and ECOC2026 | VCSELs already hit ≤1 pJ/bit; fiber is what holds them back, slow-and-wide never lost on the emitters; it lost on fiber count and assembly.

LightXcelerate's response is a 19-core MCF co-designed with YOFC, so the layout of each VCSEL subarray matches the layout of the fiber cores one-to-one. Three MCFs placed in the V-grooves of a fiber array align all 57 channels.

▲ The 19-core multicore fiber co-designed with YOFC: three MCFs align to 57 micro-VCSELs, and one MCF replaces 19 fibers (Image source: LightXcelerate | 2026 OCP Global Summit presentation)

Scale this to a 1.6T link (STT estimate at 32G): 50 lanes each way, 100 cores in total. The conventional approach needs 100 fibers; a 19-core MCF needs 6.

▲ A 57-lane chip goes from 57 fibers to 3 MCFs, and a 1.6T link from 100 fibers to 6, cutting fiber count to roughly 1/17 to 1/19 (Image source: Simple Tech Trend original; data from LightXcelerate, 2026 OCP Global Summit presentation)

Compare Credo at the same OCP: its 1.6T ZeroFlap ALC (active light cable) needs about 200 fibers per cable, and Credo's answer is a blind-mate optical backplane at the system level, managing fiber as backplane wiring. LightXcelerate works from the other end: instead of managing more fibers, it makes each fiber carry 19 channels. The two approaches do not conflict. The backplane addresses wiring inside the rack, while MCF addresses the number of coupling points at the chip edge; the first saves assembly labor, the second also cuts the number of fiber arrays, connectors and cleaning points.

Two more details came out in Q&A. The VCSEL itself is single-mode (3–4 µm aperture, ~10 µm beam), but the fiber core is 20 µm graded-index, with only a few modes, chosen to relax alignment tolerance. The fiber is glued directly onto the VCSEL die (butt coupling), so the optical interface is protected once it is bonded.

4. The scorecard: measured, simulated, and drawn

This is the part of the talk that deserves the closest reading. LightXcelerate gave many numbers, but their maturity differs completely.

Measured:

• DC: threshold ~1.1 mA, ~3.5 mW output at 6 mA, slope efficiency ~0.7 W/A

• High speed: S21 bandwidth ~20 GHz at 7 mA; 25 Gb/s eye with 23.1% mask margin and 2.39 dB ER; 32 Gb/s mask margin drops to 5.5%, ER 1.88 dB (PRBS7, 0.7 Vpp)

• Reliability: voltage flat to ~1,200 h at 125°C / 9 mA; optical power run to 6,000 h at 85°C / 10 mA, with some samples falling to about 90%; 12 samples at 165°C junction temperature run to 1,000 h, normalized power roughly between 95% and 107%

▲ Micro-VCSEL HTOL reliability: 125°C / 9 mA and 85°C / 10 mA out to 6,000 hours, and Tj 165°C out to 1,000 hours (Image source: LightXcelerate | 2026 OCP Global Summit presentation)

Simulated: < 1.5 pJ/bit. Pressed in Q&A, the speaker confirmed it is a simulated value based on the driver and TIA designs, about 0.9 pJ/bit on Tx with the rest on the TIA; how energy scales from 32G to 64G is "something we can figure out later."

Roadmap: 64G, 100G and 200G per lane.

▲ LightX-1 data maturity: DC, 32G eye diagrams and HTOL are measured, 1.5 pJ/bit is simulated, and 64G and above are roadmap (Image source: Simple Tech Trend original; data from LightXcelerate, 2026 OCP Global Summit presentation)

A 5.5% mask margin means 32G is already near the limit of this package version. The speaker said the bandwidth limit currently comes from packaging: resistance in the copper pillars and flip-chip bond causes peaking in the frequency response, which they are addressing. In other words, the next milestone is not a new VCSEL; it is a new package.

5. Risks and counterarguments

• Energy not measured: 1.5 pJ/bit is simulated; Credo's figure for µVCSEL links at the same OCP is < 2 pJ/bit. The two cannot be ranked until both are measured.

• Wavelength not disclosed: neither the slides nor the transcript give the wavelength. As we saw in ECOC2026 | 850nm arrays all failed by 1,600 hours, 1060nm ran 5,000 hours with zero failures, VCSEL array reliability depends heavily on wavelength; this is the missing piece when reading the 6,000-hour data.

• MCF moves the bottleneck to fan-out and connectors: the speaker said the VCSEL-to-fiber-array coupling is proprietary, after which standard connectors can be used. But multicore fiber connectors need rotational alignment, and on field mating and dust the team admitted it "doesn't have much data."

• Modal noise in few-mode fiber: one Q&A question directly challenged whether 20 µm graded-index fiber has enough mode diversity; the speaker only said "we tested it, there are a few modes," without BER or reach data.

• Density metric does not match hyperscaler specs: Microsoft's optical I/O target is > 10 Tbps/mm (see ECOC2026 | Microsoft wrote down the spec sheet for optical I/O), measured per mm of chip edge. LightXcelerate only gave die area, not a number on that basis, so there is no direct way yet to check how far it is from the target.

6. What it means for Taiwan's supply chain

• No Taiwanese companies appear on the slides. The only named partner is YOFC; the funding slide names NVIDIA, Lumentum, Coherent, Marvell, Celestial AI, Meta and Corning.

• The process flow speaks Taiwan's language. LightXcelerate stresses that every step is "OSAT-ready": Cu-pillar flip-chip of III-V dies, underfill, TSVs through the EIC, 12-inch interposers, passive mechanical alignment. These are strengths of Taiwan's advanced packaging and OSAT industry. The company has not named packaging or foundry partners; if it moves to volume, Taiwanese OSATs are natural candidates, but that only counts once it is announced.

• Taiwan's VCSEL epi and foundry players should watch the spec, not this company. Single-mode, 3 µm aperture, backside emission, 165°C junction-temperature qualification form a template for micro-VCSELs. If slow-and-wide moves to multicore fiber, the VCSEL array layout becomes bound to the fiber-core pattern, and device design and fiber design will be fixed together, a new challenge for suppliers that only make devices.

• For the MCF and fan-out segment, no Taiwanese participant appeared in this talk.

7. Conclusion

The value of LightXcelerate's talk is that it pulls the slow-and-wide question back to its most practical point: not whether the emitters are fast enough, but how many fibers one chip has to connect. Matching the VCSEL pattern to a 19-core fiber is the most direct fiber-count solution we have seen this year.

But maturity has to be read honestly. What is measured is 32G NRZ with 5.5% eye margin; 1.5 pJ/bit is simulated; 64G and up is roadmap. Over the next 12 months, watch three things: when a 64G eye is published, when pJ/bit moves from simulated to measured, and whether MCF connectors enter OCP or MSA standards discussions.

Slow-and-wide's bottleneck is fiber count. LightXcelerate has shown it can be solved at the coupling interface, but it has not yet shown this engine can run fast enough.

This article is for technology and industry trend analysis only and does not constitute investment advice.