OCP Global Summit 2026 | Celestica | Tareq Bustami, Manish Mehta, Binbin Guan | Designing the Next AI Fabric

1. One Talk That Strings Compute, Optics and Systems Together

Celestica hosted the session in three parts: Binbin Guan of OpenAI on compute requirements, Manish Mehta of Broadcom on optics, and Tareq Bustami of Celestica closing on system integration. Bustami's opening premise: compute is growing 10x every two years, far beyond what Moore's law delivers, so further gains must come from the system, and optics is the "sandbox" system designers most need to widen.

Taken together, the storyline is clear: the buyer defines the metrics, the chip vendor defines the interface, and the system builder absorbs the complexity.

2. Breaking Down OpenAI's Yardstick: Latency and Energy per Token

OpenAI first set out the scale of demand: ChatGPT weekly users passed 1 billion on August 31, 2026, and Codex weekly users passed 5 million in July. It then reduced what matters for an AI network to two metrics:

• User experience: request latency, defined as TTLT (time to last token), with TBT (time between tokens) as another useful proxy.

• Inference efficiency: energy per request, measured as energy per token or tokens per joule, with energy treated as a proxy for cost.

▲ OpenAI uses TTLT and tokens/joule as its two key metrics, and lists chip count, per-chip throughput and TTFT as non-goals (Image source: OpenAI | 2026 OCP Global Summit presentation (03:41))

The two often pull against each other: cutting latency by an order of magnitude usually costs more energy. OpenAI then split a single request into three hardware regimes:

Phase	Main bottleneck	Comms pattern
Prefill (encode context)	FLOPs and attention, low memory-bandwidth demand	Smooth, easy to schedule
Draft model (speculate)	Network latency, small models, ultra-low batch	Latency bound
Spec-verify (decode)	Attention needs compute, MoE needs HBM bandwidth	Bursty

The conclusion sits at the bottom of the slide: what matters is requests per second per watt at the required SLA latency. That matters for optics vendors: a solution that chases bandwidth and ignores latency is out of the game in the draft-model phase.

3. Breaking Down Jalapeño: Copper Holds 128 Chips, Optics Handles 2,048

At the end of August OpenAI announced Jalapeño, its first in-house ASIC. Inside the chip the rule is "keep common operands local": each of 64 core slices is paired with an HBM slice, linked by a high-bandwidth, low-latency collective network, plus a slower but more flexible general NoC that reaches the outside network through a scale-up Ethernet bridge.

At rack level, host and accelerator racks are deployed as pairs, in a "half-flattened" two-level Clos topology:

• Local domain: up to 128 Jalapeños connected through Broadcom TH6, over copper, serving high-bandwidth, low-latency work.

• Global domain: up to 2,048 Jalapeños across eight TH6 rails, over optics for rack-to-rack communication.

▲ Jalapeño's two-tier network: a 128-chip local domain runs on copper, then scales through 8 TH6 rails to a 2,048-chip global domain on optics, a 16x difference in scale (Image source: Simple Tech Trend original, data from OpenAI's 2026 OCP Global Summit presentation)

The split follows the workload: tensor parallelism needs high bandwidth, expert parallelism needs less, and both need low latency. This matches the view in 2026 OCP APAC Summit | SemiAnalysis | Scale Up Sophistry: copper has not lost the shortest, densest links; the optics battle is the stretch that makes scale-up 16x larger.

4. Broadcom: Moving Optics From Scale-Out Into Scale-Up

Mehta was direct: most of the optical bandwidth that exploded in recent years went into scale-out, using pluggable modules with fully retimed DSPs; the next step is bringing optics into scale-up, which is served by copper today and needs far more bandwidth.

He sorted the components into five blocks: VCSEL (multimode, short reach), EML (single mode, long reach), CW lasers (single-mode sources for silicon photonics and CPO), CPO (aimed at scale-out) and OCI (aimed at scale-up). Broadcom's own CPO roadmap:

Year	Product	Switch capacity	Per lane
2022	TH4 Humboldt	25.6T	100G
2024	TH5 Bailly	51.2T	100G
2026	TH6 Davisson	102.4T	200G
2028	OCI	Next Gen	Not disclosed

We covered the reliability data of the third CPO generation in 2026 OCP APAC Summit | Broadcom | CPO's Third-Generation Report Card. This time Mehta added the volume challenges: high-density PIC-to-EIC stacking must support 400G direct drive; each chip package must connect more than 1,000 fibers, with detachable connectors so the package can go through reflow; and automation, where Broadcom showed purpose-built equipment such as a support frame, in-line OGP metrology and Z-spring delatching, aiming for optical engines co-packaged with the ASIC without human touch.

5. Breaking Down OCI: Electrical Lanes Run Out of Road, So Go Wide

OCI-MSA was established in March 2026 with founding members Meta, Microsoft, OpenAI, AMD, Broadcom and NVIDIA, with the goal of moving scale-up from a single rack to multi-rack and multi-row. For spec details see Tech Analysis | Meta, Broadcom and AMD Define the OCI 200G Line Spec.

The most informative slide was Broadcom asking itself whether OCI-MSA addresses scaling:

• 200G: 100Gbaud PAM4 on both the electrical and optical side, linear drive works, available today.

• 400G: 200Gbaud PAM4 optical, electrical PAM4/6/8 or SBD still a question mark, linear is a "maybe", spec timing "2027?", with a note on diminishing returns in IC area and pJ/bit.

• 800G: timing ">2030?", linear "unlikely".

▲ The faster each lane, the harder linear direct drive becomes; OCI Gen1 instead uses 4 wavelengths × 50G NRZ bidirectional transmission, with the Gen2 400G spec in 2027 and Gen3 800G in 202x (Image source: Simple Tech Trend original, data from Broadcom's 2026 OCP Global Summit presentation)

OCI Gen1's answer is wide parallel, 4λ × 50Gbps NRZ, DWDM, bidirectional, sidestepping the high-speed SerDes challenge. Broadcom's target is "copper-level power, better-than-copper latency", and it said announcements on the first OCI silicon will come in the next few months.

6. Celestica: The Bottleneck Has Moved to the Rack and to Validation

Bustami got straight to it: the rack itself has become the bottleneck. Liquid cooling has been added and PCBs reach 50 layers, but underneath it is still a pluggable architecture. The complexity listed on the slide:

• About 5,000 passive copper cables in one scale-up rack, with rack power around 1 MW

• Signal integrity challenges at 224G, and copper reach shrinking at 1.6T, driving the move to optics

• Rack weight around 4,000 lb today, with an 8,000 lb design target ahead

▲ Optical module qualification cycles: 36 months for 100G/400G, 24 months for 800G and 18 months for 1.6T, while AI accelerators turn over every year (Image source: Celestica | 2026 OCP Global Summit presentation (16:33))

The other side is time compression: qualification windows have shrunk from 36 to 18 months, and 70% of Celestica's engineering resources go into validation. Its 2027 to 2030 migration has three steps: deploy CPO first in scale-out (Bustami cited Meta's results on TH5 Bailly, with reliability even better than pluggables); then add optical repeaters next to TH6 trays to extend scale-up; and finally native OCI XPUs or scale-up switches that drive optics directly.

On manufacturing, Celestica is building an end-to-end flow: thick, heavy CPO devices need new pick-and-place equipment, fiber array units (FAU) must be assembled in clean rooms, plus end-to-end optical test and hot-gas rework. On product, there is the DS6005:

▲ Celestica DS6005: a 1.5OU, 64-port 1.6TbE CPO switch based on Broadcom Tomahawk 6 Davisson, to be contributed to OCP (Image source: Celestica | 2026 OCP Global Summit presentation (19:01))

The DS6005 runs SONiC and is in EVT, with full production in 2027 stated verbally. We discussed Celestica's relationship with OpenAI in Earnings Highlights: Celestica (CLS) | Q2 FY2026; this talk lays that customer relationship out on the technical side.

7. Risks and Counterarguments

• 2,048 chips is a design ceiling, not a deployment number. OpenAI gave no optical power, latency or actual deployment scale for the global domain.

• OCI's timeline is itself a question mark. Broadcom's own table marks 400G as "2027?" and 800G as ">2030?", with Gen3 only listed as 202x.

• The DS6005 2027 production date was stated verbally; the slides show only EVT and the plan to contribute to OCP, with specs and power not yet public.

• Copper is not leaving. OpenAI explicitly chose copper for the local domain, meaning scale-up optics must first prove itself between racks before moving inside them.

• Validation effort is a hidden cost. With 70% of engineering spent on validation, this share will only rise if CPO brings optical failure modes onto the main board.

8. What It Means for Taiwan's Supply Chain

• The talk named no Taiwanese companies; what follows reads only from the process steps listed on the slides.

• CPO assembly shifts from "plugging modules" to "package-level manufacturing". The slides list FAU/CPO inspection and cleaning, SMT optical validation, clean-room assembly and hot-gas rework. System assemblers that want CPO switch business must reinvest in their lines, which Celestica is already doing.

• Fiber connectors with more than 1,000 fibers, detachable and dust resistant are one of the three challenges Broadcom named; Taiwanese fiber jumper and connector makers should check their position against that requirement.

• The bar for white-box switch makers is rising. Celestica is making a TH6 CPO switch an open OCP design, so in the CPO generation Taiwanese white-box makers compete not only on shipment speed but on validation and optical process capability.

9. Conclusion

The key takeaway is the division of labor: OpenAI defines the problem in latency and energy per token, keeping copper within 128 chips and using optics only at 2,048; Broadcom concedes that faster lanes make linear drive harder, so OCI goes slow and wide; Celestica says the real bottleneck is now rack weight, copper cable count and an 18-month qualification window.

Keep the timing separate. In 2026 we see TH6 Davisson 102.4T CPO and scale-out deployments; scale-up optics waits for the OCI Gen2 spec (2027) and native OCI silicon, which Broadcom's own roadmap places in 2028. Three things to watch over the next 12 months: when Broadcom announces its first OCI silicon, whether OpenAI discloses global-domain optical power, and whether DS6005 moves from EVT to production on time.

Optics will win scale-up not by being faster than copper, but by growing the domain 16x within the latency budget, and by letting system builders validate it in time.

This article is for technology and industry trend analysis only and does not constitute investment advice.