ECOC 2025 Tech Focus: Cisco on Switch Design for the Terabit Era
Updated: 21 hours ago
Introduction
With the rise of AI factories and hyperscale data centers, networking is entering the Terabit era. This isn't just a speed increase (100G → 200G → 400G/lane); it represents a deep transformation of the whole system in power, thermal design and interconnect technology. In its ECOC 2025 talk, Cisco shared its view of switch architecture, covering ASIC evolution, the trade-offs between copper and optical interconnect, the feasibility of 400G SerDes and the coexistence of CPO and pluggables.
Content
1. From Front-End Networks to AI Factories: How Requirements Have Evolved
Front-end networks: traditionally CPU-centric and limited in scale.
AI factories: GPUs are the compute core and must emulate a "single giant processor," driving scale-up (high-speed GPU interconnect within a rack) and scale-out (cluster connectivity across racks).
Challenge: every doubling of speed comes with a sharp increase in ASIC capacity, I/O density and cooling requirements.
2. ASIC Evolution and the Power Challenge
Historical path: from 640G ASICs to 400T ASICs, roughly 640× growth.
Power trend: total power rose ~119×, far less than capacity growth, showing improved efficiency.
Bottleneck:
The ASIC itself benefits from Moore's Law, improving about 42×.
Interconnect (I/O) power, however, has risen ~175× and become the main source of pressure.
👉 Key observation: the real challenge for switches isn't ASIC design but how to "get the data off the chip."
3. Copper vs. Optics: Trading Off Power and Reach
Copper (DAC/ACC):
Lowest power, suited to short reach (chip-to-chip, within a rack).
Clear reach limitations.
Optics (Pluggable / CPO):
Suited to medium and long reach, at the cost of higher power.
Power and reach form a trade-off.
New approaches:
LPO/LRO: partially linear solutions that reduce power.
CPO: shared lasers and fewer retimers improve efficiency.
4. Design Differences Between Scale-Up and Scale-Out
Scale-Up (within a rack):
Requirements: high density, short reach, low latency.
Solution: many lanes, copper first, combined with short-reach optics where needed.
Thermal: liquid cooling is becoming a necessity.
Scale-Out (across racks/data halls):
Requirements: medium-to-long reach and scalability.
Solution: relies mainly on optical transmission (IMDD / coherent), with pluggables and CPO coexisting.
Cooling: must support both air and liquid cooling, so module designs have to adapt to different facility conditions.
5. The Need for 400G SerDes
Status: 200G SerDes is being deployed, and 400G SerDes is the inevitable direction for the Terabit era.
Challenges:
Requires a new generation of connectors; existing OSFP/QSFP-DD can't support it.
The electrical and optical interfaces must be considered together to avoid fragmenting the industry into multiple incompatible specs.
Power and signal integrity will be the key design factors.
6. A Dual Track for CPO and Pluggables
CPO: high power efficiency but low flexibility; the decision must be made at the ASIC design stage.
Pluggable: highly flexible, suits a variety of scenarios, and will remain for a long time.
Cisco's view: the two will coexist, and future systems must support copper + optics and CPO + pluggable at the same time, forming a "dual-track architecture."
Conclusion
Cisco's talk emphasized that switch design in the Terabit era is a system-level, multi-faceted challenge:
ASICs keep evolving, but I/O and power are the bottleneck.
Copper and optics will coexist for the long term, with the best option chosen by reach and efficiency.
400G SerDes and new connectors are the industry's key tasks for the next five years.
CPO and pluggables will coexist, and real deployment must weigh economics, architecture and market convergence together.
The talk is a reminder to the industry that technical breakthroughs must come back to economic and architectural reality. Only by balancing power, reliability and cost can Terabit-era switches truly become the infrastructure of AI factories.
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