Paper Analysis | iPronics Uses Graph Theory to Benchmark Silicon Photonics OCS: At 128×128 High Radix, Double Dilated Benes Is the Design You Can Build Today

2 days ago

6 min read

1. Who Published This and Why It Matters

The authors are from iPronics Programmable Photonics (a programmable photonics startup based in Valencia, Spain; co-founder Daniel Pérez-López is a co-author), and the paper is published in Journal of Lightwave Technology (JLT).

Why does it matter? Because optical circuit switching (OCS) is a key piece of the scale-up / scale-out puzzle in AI data centers — it cuts latency, saves power and adds bandwidth by never converting light back to electrical signals. So far, MEMS OCS (the Google Apollo camp) is in volume production, reliable and cheap — the money-maker of today; but MEMS relies on mechanical movement, which limits reconfiguration speed and reliability. Silicon photonics OCS (using Mach-Zehnder interferometers, MZIs, as 2×2 switch cells) has no moving parts, reconfigures fast and can be mass-produced, so it is widely tipped to take over. Yet whether it can reach a high radix of 128 has never been systematically answered.

We covered the MEMS vs. SiPh OCS debate in OCP 2026 white paper: OCS moves from Google's in-house patent into the whole data center industry's toolbox and Google dissects its TPU, and the hidden hero called optical switching. This iPronics paper fills in the other side — turning architecture selection into a computable benchmark.

Modeling the optical switch network as a graph — a 4×4 Benes circuit with MZIs as 2×2 switch cells, its graph representation, and the architectures studied (Dilated Benes / Double Dilated Benes / PILOSS / Dilated Banyan). Source: iPronics, JLT 2026 - Figure 1

2. The Core Question: Which Architecture Scales to 128×128 While Balancing All Three Metrics

In one sentence: With today's silicon photonics processes, which OCS architecture can scale to a 128×128 high radix while balancing loss, SNR and blocking?

iPronics models each network as a graph (nodes = switch cells / crossings, edges = waveguides), then runs pathfinding algorithms directly on the graph for routing and blocking analysis. This lets four metrics — hardware complexity, optical loss, SNR and blocking — be computed in a single framework, instead of picking an architecture by intuition.

Two routing strategies are included: random (random path selection) and sorted (minimum index, systematically favoring upper paths). The focus is on asynchronous switching, which reflects unpredictable real-world IO requests — a worst-case stress test.

3. Key Figures, One by One

3.1 Hardware Complexity: Benes-like Is O(N log N), PILOSS / Dilated Banyan Are O(N²)

This figure shows how switch cell count, stage count and crossing count grow with radix across the five architectures. Benes-like networks grow as O(N log N) (double the radix, roughly double the cells); PILOSS and Dilated Banyan grow as O(N²) (double the radix, four times the cells).

The result is brutal: Dilated Banyan needs more than 32,000 switch cells at 128×128, while Benes-like networks need only 12–16 stages. Double Dilated Benes, however, has the most extreme crossing count — a worst-case path at 128×128 crosses nearly 700 waveguides (about 360 on average), the price it pays for its higher path diversity.

Figure 3: Hardware complexity — (a) switch cell and stage counts per architecture (radix 8–128); (b) distribution of waveguide crossings traversed per path. Source: iPronics, JLT 2026 - Figure 3

3.2 Optical Performance: Dilated Banyan Has the Best SNR, PILOSS Collapses at High Radix

This figure shows SNR and loss for the five architectures. Dilated Banyan delivers SNR >50 dB (still >40 dB across the entire O-band even at 64 ports), the best of the group; standard Benes is the worst (around 10 dB at the low-radix corner wavelengths); PILOSS sees its SNR collapse at high radix as the number of stages, and with it the crosstalk sources, explodes.

On loss (using the Table I component parameters: switch cell 0.2 dB, crossing 0.002 dB, edge coupler 0.5 dB, polarization components 0.4 dB, waveguide 0.5 dB/cm): Benes has the lowest loss, Dilated Banyan stays <6 dB at 128×128 and the Dilated family <7 dB; meanwhile PILOSS loss shoots past 25 dB at 128×128, and only stays <10 dB up to 32×32.

Figure 4: Optical performance — (a) extinction ratio (ER) of switch cells and crossings; (b) SNR vs. wavelength and radix per architecture; (c) box plots of PIC loss by radix and architecture. Source: iPronics, JLT 2026 - Figure 4

3.3 Blocking: Double Dilated Benes Is the Strongest of the Benes Family

This figure shows blocking behavior under asynchronous switching. WSNB / SNB topologies (PILOSS, Dilated Banyan) guarantee that any idle IO pair can be connected without blocking; RNB topologies (Benes, Dilated Benes) may block. The paper runs both incremental and dynamic experiments and distinguishes conflict 1 (shared edge → blocking) from conflict 2 (shared node → first-order crosstalk, a stricter condition).

Key conclusion: Double Dilated Benes shows zero blocking under conflict 1 and low blocking under conflict 2; in the harshest dynamic setting (arrival rate = 1, conflict 2, sorted), its per-request blocking at 128×128 stays below 0.04, while standard Benes / Dilated Benes block almost everything. Sorted routing blocks less than random — a smart routing algorithm is itself part of how far an architecture can scale.

Figure 6: Blocking in the dynamic experiment — per-iteration (PI) and per-request (PR) blocking vs. connection duration; Double Dilated Benes clearly outperforms the other Benes-family architectures. Source: iPronics, JLT 2026 - Figure 6

4. Technical Highlight: Turning "Pick an Architecture" into a Math Problem

The biggest contribution is not any single number but turning OCS architecture selection from rule-of-thumb into a reproducible graph-theory benchmark. Five architectures, radix 8–128, two routing strategies, two conflict definitions, incremental and dynamic experiments — all run through the same graph model.

The second highlight is identifying the sweet spot: Table II puts hardware, optics and blocking side by side, and concludes that Double Dilated Benes strikes the best balance among 128 radix, manufacturable die area and acceptable blocking.

Table II: Summary of the five architectures — hardware complexity (cells / crossings / die mm²), optical performance (loss / SNR), and blocking type and level. Source: iPronics, JLT 2026 - Table II

5. Industry Implications: What Can Be Built Today, and What Has to Wait

iPronics started out building programmable photonic processors (FPGA-like reconfigurable photonic circuits). In this paper it applies its in-house graph-theory / auto-routing tools to benchmark OCS designs — a showcase for its tools and IP, not a sign that it plans to mass-produce OCS itself.

What can be built today: at 128×128, choose Double Dilated Benes — today's silicon photonics processes can deliver <7 dB loss, >45 dB SNR, ~150 mm² and low blocking. At low radix (≤32), Dilated Banyan is best (SNB, SNR >50 dB).

What has to wait: taking Dilated Banyan to 128 radix needs a big process leap — the paper estimates that 128×128 requires switch cell loss down to 0.15 dB and crossing loss to 1.5 mdB; 256×256 needs 0.1 dB and 1 mdB. Note also that these are crosstalk-limited SNRs, not white-noise SNRs; the paper uses the >30 dB OSNR required for PAM-4 100 Gbps (BER <1×10⁻⁴) as a reference benchmark.

For the industry context of this scale-up / OCS path, see SiPh interposer is the endgame architecture for scale-up.

But don't get carried away. An honest sense of distance: this is simulation / benchmarking, not taped-out silicon; Double Dilated Benes is still RNB (it blocks, so it needs admissible-blocking tolerance plus scheduling); thermo-optic phase shifters have a large footprint (hundreds of μm), and while TFLN / phase-change materials can shrink the footprint and push reconfiguration to ns, that is another layer of engineering.

6. Conclusion

The value of this iPronics paper is that it takes the yes-or-no question "can SiPh OCS reach high radix?" and reframes it as an engineering selection question: which architecture? The answer is clear: low radix (≤32) goes Dilated Banyan; high radix (128) goes Double Dilated Benes today; avoid PILOSS beyond 32; standard Benes only fits scenarios that can tolerate blocking.

For anyone evaluating OCS (buyer or builder), the actionable takeaway is — break the binary "SiPh OCS vs. MEMS" question into a three-axis decision: radix × architecture × blocking tolerance. The window for SiPh OCS is not gated by "can it be done" but by "is the right architecture chosen". That is exactly where tool-centric players like iPronics add value.

References

Luis Torrijos-Morán, Zhenyun Xie, Celestino Bixquert-Marrades, Iñigo Belio-Apaolaza, Daniel Pérez-López, "Scalability Analysis of Silicon Photonics Optical Circuit Switch Architectures," Journal of Lightwave Technology (accepted). DOI: 10.1109/JLT.2026.3705998. Affiliation: iPronics Programmable Photonics SL (Spain). Funding: ERC Starting Grant (LS-Photonics), HORIZON-EIC (EXCITE).