OCP 2025 APAC Summit: Technology and Industry Takeaways

Summary

At the OCP 2025 APAC Summit, representatives from leading players including Meta, Broadcom, Astera Labs, TSMC, ASE, the UALink Consortium and Digitimes shared in-depth views on the architectural transformation of data centers and high-performance computing in the AI era, open standards, interconnect technology, advanced packaging and optoelectronic integration. The summit showed how the explosive growth in AI model size and compute demand is pushing data centers to evolve from server-level to rack-scale design.

Going forward, high-bandwidth, low-latency interconnect (PCIe Gen6, CXL3, UALink, UEC), optoelectronic integration (CPO, COUPE, CoWoS) and open standards will become the three pillars supporting AI and HPC — and will reshape the supply chain and how the industry collaborates.

Details

1. The Twin Engines of AI Compute Architecture: Scale-Up and Scale-Out

• Meta analyzed AI model training needs spanning regions and data centers, noting that large language models (LLMs) and multi-step reasoning require lower-latency, higher-bandwidth inter-node communication.

• Broadcom framed the discussion around a "Compute–Memory–Networking triangle," explaining that compute scaling cannot rely on a single architecture:

  • Scale-up: multiple GPUs/accelerators share a unified memory space, reducing data-copy cost and latency — suited to tightly coupled model training and real-time inference.

  • Scale-out: multiple nodes compute cooperatively over high-speed networks — suited to large-scale distributed training and batch inference.

• Panel consensus: future data centers will deploy a mix of both, dynamically switching and allocating resources by workload.

2. The Key to Breaking Proprietary Ecosystems: Open Standards and Interoperability

• UALink Consortium's open accelerator interconnect standard is designed to replace or complement closed protocols such as NVLink, enabling direct interoperability among GPUs, ASICs and AI accelerators from different vendors.

• Ultra Ethernet Consortium (UEC) focuses on Ethernet-based scale-out networking, complementing UALink at a different layer.

• Technical highlights:

  • Open standards reduce vendor lock-in risk and foster competition and innovation.

  • Standards must balance high performance with software ecosystem support (MPI, deep learning frameworks).

  • Cross-consortium collaboration (UALink + UEC) could form a complete HPC/AI interconnect solution.

3. High-Speed Interconnect and Memory Expansion: PCIe Gen6 and CXL3 Come to Market

• Astera Labs showcased PCIe Gen6 and CXL3 in rack-scale architectures:

  1. PCIe Gen6: delivers up to 64 GT/s, symmetrically supporting high-speed direct links among GPUs, FPGAs and all kinds of accelerators.

  2. CXL3: supports memory pooling and dynamic allocation, letting multiple compute nodes share high-bandwidth, low-latency memory resources.

  3. PCIe Gearbox technology: solves interoperability between PCIe generations and lowers upgrade costs.

• Measurements show CXL memory can reduce AI inference latency and raise GPU utilization, improving LLM performance per watt and TCO.

4. Advanced Packaging and Optoelectronic Integration: Breaking Bandwidth and Power Bottlenecks

• TSMC:

  • CPO (Co-Packaged Optics) and COUPE technologies integrate optical I/O directly into the switch chip package, significantly cutting I/O power and latency.

  • Combined with CoWoS high-bandwidth packaging, they support higher channel density and better-optimized thermal design.

  • Target applications include AI data center switches and HPC nodes.

• ASE:

  • Introduced modular advanced packaging solutions that allow more flexible combination of optoelectronic components and logic chips.

  • Stressed that package design must be co-developed with system architecture to address the thermal challenges of high power density.

5. Restructuring the AI Supply Chain: Modularity and Vertical Integration in Parallel

• Digitimes reported that the AI infrastructure supply chain is rapidly shifting from a traditional linear division of labor to a hybrid of modularity and vertical integration:

  • Modularity: system vendors prefer upgradable modular platforms to reduce the retrofit cost of technology refreshes.

  • Vertical integration: some leading players are integrating design, manufacturing, packaging and module assembly to lock up key technologies (such as high-speed interconnect and optoelectronic packaging).

• Core changes:

  1. High-speed interconnect and memory technologies are becoming supply chain control points.

  2. Optoelectronic integration is driving more cross-domain collaboration (semiconductors, packaging, networking equipment).

  3. Cloud service providers (CSPs) are directly involved in hardware design to optimize their own AI workloads.

Conclusion

This year's OCP 2025 APAC Summit clearly outlined four future directions for AI data centers and high-performance computing infrastructure:

1. Rack-scale architecture leads compute design: replacing the traditional server-centric model and improving efficiency through hybrid scale-up/scale-out.

2. Open standards become the core of interoperability: UALink and UEC could reshape the HPC and AI interconnect ecosystem.

3. High-speed interconnect and memory technologies evolve in tandem: PCIe Gen6, CXL3 and Gearbox technology will change how accelerator resources are scheduled.

4. Advanced packaging and optoelectronic integration reach deployment: CPO, COUPE and CoWoS will tackle bandwidth and power bottlenecks together, becoming the foundation of next-generation switching and compute platforms.

   
   
   
   

What to watch over the next 12–24 months:

• Progress on UALink/UEC interoperability testing and industry adoption.

• Deployment cases of PCIe Gen6/CXL3 in commercial data centers.

• Volume production timelines for CPO and optoelectronic modules.

• New collaboration models in the AI supply chain around modular platforms and advanced packaging.

Summary Table of Key Presentations by Company

Company / Organization	Technology Area	Core View	Potential Impact
Meta	Distributed AI network architecture	As AI models keep growing, they need lower-latency, higher-bandwidth cross-node communication; emphasizes scale-out and geographically distributed collaboration.	Drives cross-data-center network optimization and increases demand for high-speed Ethernet and open interconnect standards.
Broadcom	Compute–memory–networking balance	Proposes a Compute–Memory–Networking triangle, mixing scale-up and scale-out to handle diverse AI workloads.	Shapes AI data center architecture strategy and drives upgrades of networking chips and switches.
UALink Consortium	Open accelerator interconnect	Defines an open standard to replace or complement NVLink, supporting interoperability among multi-vendor GPUs/ASICs/AI accelerators.	Could reduce vendor lock-in risk and drive competition and ecosystem diversity in the accelerator market.
UEC (Ultra Ethernet Consortium)	Standardized scale-out networking	An Ethernet-based open networking standard that complements UALink at a different layer.	Improves interoperability of HPC and AI scale-out architectures and the efficiency of large-scale deployments.
Astera Labs	High-speed interconnect, memory expansion	PCIe Gen6 and CXL3 enable memory pooling and low-latency interconnect; Gearbox technology lowers upgrade costs.	Changes how accelerator and memory resources are scheduled, improving GPU utilization and TCO.
TSMC	Advanced packaging and optoelectronic integration	Combines CPO, COUPE and CoWoS for high-density channels and low-power optical I/O, targeting AI switches and HPC nodes.	Drives volume production of optoelectronic integration, bringing next-generation designs to data center switches and HPC equipment.
ASE	Modular packaging strategy	Co-develops packaging with system design to address thermal and bandwidth challenges at high power density.	Increases flexibility in AI module design and accelerates heterogeneous integration.
Digitimes	Industry supply chain analysis	In the AI era, the supply chain is shifting from a linear division of labor to modularity and vertical integration in parallel.	Reshapes supply chain collaboration and market leadership, spurring more cross-domain alliances.