OCP Global Summit 2026 | OIF | Jeffrey Hutchins, Sam Kocsis | Energy Efficient Interfaces: OIF Is Enabling the Next Generation of AI

1. From Requirements Document to Blueprint

In OIF Draws the Official Map for AI Interconnect we broke down OIF's 2024 "System Vendor Requirements for Energy Efficient Interfaces": AI interconnect split into three networks, with short-reach, high-density use cases asking for 5 or even 3 pJ/bit. That was a buyer's wish list.

At the OIF Workshop at OCP Global Summit, the speakers were Jeffrey Hutchins (Ranovus CTO's Office), Vice Chair for Energy Efficient Interfaces in OIF's Physical & Link Layer Working Group, and Sam Kocsis (Director of Standards and Technology, Amphenol), Chair of the OIF Technical Committee. They presented two years of progress in turning the wish list into documents:

• Published: Compute Optics Interface (COI) white paper (2026/3/9), EEI framework document, 112G RTLR implementation agreement, HD Connector Framework (2026/5/19)

• In progress: 224G RTLR and the 12.8 Tb/s NPO module

• Earlier groundwork: the 3.2T CPO module started at the beginning of the decade, plus the ELSFP external laser source implementation agreement

Two years ago OIF asked "what do you need"; now it is answering "what will it look like".

2. Power Breakdown: Scale-Up Is the Main Battlefield

Hutchins used a hypothetical optically enabled 72-GPU pod to show where the power goes. The configuration table is blunt: scale-out is 72 links at 800G, 57.6 Tb/s in total; scale-up is 2,592 links at 400G, 1,036.8 Tb/s in total, about 18 times scale-out (STT calculation from the table; the slide says about 10x).

Energy per bit for the four interface types: CPO 4, LTLR (linear transmit, linear receive) 6, RTLR 10, RTRR (fully retimed) 15 pJ/bit. Applied to the scale-up bandwidth, STT estimates the optical power as:

Interface	pJ/bit	Scale-up optical power (STT estimate)
CPO	4	~4.1 kW
LTLR	6	~6.2 kW
RTLR	10	~10.4 kW
RTRR	15	~15.6 kW

Moving from RTRR to CPO saves about 11.5 kW per 72-GPU pod, roughly 13% of the pod's non-optical power (about 85 kW). OIF's conclusion: RTLR and linear electrical interfaces are the practical path to lower power.

▲ Power of a hypothetical 72-GPU pod, from CPO at 4 pJ/bit to RTRR at 15 pJ/bit; scale-up dominates rack interconnect power (Image source: OIF | 2026 OCP Global Summit presentation (02:50))

The RTLR design logic is worth spelling out: the transmit side retimes before the optics, while the receive side relies on the host SerDes. This tolerates higher-loss electrical channels without putting another DSP in the module on the receive side. It is a compromise between LPO (fully linear) and full retiming; the 112G version is published and the 224G version is in progress.

3. Coordinates Breakdown: Why the 12.8T NPO Sits in the Middle

Kocsis's key slide comes from the "Energy Utilization vs Density" chart in the COI white paper. The x-axis is bandwidth edge density (Tx+Rx divided by chip edge length) and the y-axis is pJ/bit:

• 1.6T OSFP pluggables all sit on the 0.14 Tb/mm line, ranging from about 6 pJ/bit non-retimed and about 11 Tx-retimed to about 17 fully retimed (read from the chart)

• The hyperscaler CPO target region: under 4 pJ/bit at 2-4 Tb/mm

• The 12.8T NPO (orange star on the chart): about 6 pJ/bit at about 1 Tb/mm, with the target written as under 7 pJ/bit and over 1 Tb/s/mm

▲ 12.8T NPO sits between the pluggable and CPO target zones: under 7 pJ/bit and over 1 Tb/s/mm (Image source: Simple Tech Trend original; data from OIF 2026 OCP Global Summit presentation)

Why not go straight to CPO? OIF's nomenclature table gives the answer. NPO is defined as optics outside the package: NPO-PCB at 0.6-1.0 mm pitch with 16-22 dB channel loss per 200G; NPO-HDI at 0.3-0.5 mm pitch with 13-18 dB. Soldered versions are interoperable but not replaceable; socketed versions can be replaced when the blade is removed. CPO sits inside the package at C4 or µbump pitch and is interoperable only at the chiplet level.

Kocsis was direct: OIF's sweet spot right now is this middle region. That matches our view in NPO Is Not an Appetizer for CPO: NPO is a long-term option that can stand on its own, be multi-sourced and be serviced.

The 12.8T NPO project scope: 200G/lane PAM4, 64x200G (with a 6.4T variant). The implementation agreement will cover mechanical specifications, electrical interconnect and pin map, the liquid-cooling thermal interface, laser source provisions, power supply requirements and optical connectors. OIF also notes the scope and technical details may still change based on member contributions.

▲ OIF EEI-12.8Tb/s NPO module project: 200G/lane, 64×200G, with scope covering the liquid-cooling thermal interface and laser source configuration (Image source: OIF | 2026 OCP Global Summit presentation (16:14))

4. Thermal Breakdown: Heat Hits the Ceiling Before Connectors Do

The line worth taking away from this talk came from Kocsis: cooling these solutions has become harder than the physical interface itself.

The density table in the HD Connector Framework first shows the ceiling for pluggables (Tb/mm):

Per-lane rate	OSFP	OSFP-XD	Y-axis HD pluggable	Z-axis HD pluggable
112G	0.035	0.07	0.13	0.25
224G	0.07	0.14	0.25	0.49
448G	0.14	0.28	0.49	0.98

Connectors still have room to scale, but heat may not keep up. The same framework charts coolable power within one OSFP cross-section: about 30 W with air, about 65 W with a cold plate and about 110 W with in-module liquid cooling; the 1.5D connector density limit is about 16 lanes and the 2D limit about 48 lanes.

▲ For the same OSFP cross-section, 5 pJ/bit already exceeds the air-cooling limit at 2D density; 12.8T NPO is estimated at about 90 W, in liquid-cooling territory (Image source: Simple Tech Trend original; data from OIF 2026 OCP Global Summit presentation)

Run the numbers: at 200G/lane and 5 pJ/bit, 48 lanes draw about 48 W, already above air cooling; a 12.8T NPO running at the full 7 pJ/bit is about 90 W (STT estimate; the actual NPO form factor differs from OSFP), above the cold-plate limit. That is why the liquid-cooling thermal interface is in the project scope. OIF has not yet published anything on cooling; Kocsis only said it is part of deployment.

5. A Moving Target: Protocols, Connectors and Optical Links Are All Changing

Hutchins was candid that all three assumptions from when this round of work started in 2024 have changed:

• Protocol: PCIe-like (2024) shifted to Ethernet-like (2025/26: UALink, UEC, SUE-T, ESUN)

• Optical connectors: MPO and VSFF shifted to expanded-beam EBO connectors (2026), raising link loss

• Optical links: IEEE-like DR, FR2, FR4 (1310 nm) shifted to OCI-MSA (2026: BiDi 4x50G/λ, 2.5 dB, 400 GHz spacing in O-band)

The economics of BiDi are simple: transmit and receive share one fiber, halving fiber count and saving on assembly and connectors. We covered the OCI spec in Meta, Broadcom and AMD Define the OCI 200G Line-Side Spec.

On reliability, Hutchins stressed that scale-up computation is synchronous: one block in error and its retransmission push tail latency up, and once retries exceed the limit you get a link flap. He cited a Meta paper at ECOC 2025: a CPO switch showed no uncorrectable codewords over more than one million 400G port-device-hours.

6. Risks and Counterarguments

• No timeline: both 224G RTLR and 12.8T NPO are marked "in progress", and neither speaker gave a completion date for the IA. OIF's own slide says it plainly: MSAs publish fast and SDOs are slower, a structural difference.

• MSAs are fragmenting the space: XPO MSA, OCI-MSA and Open CPX all occupy the same ground, and OIF itself named XPO. We saw the speed advantage of MSAs in Ciena Turns the 6.4T Optical Engine Back into a Shelf Part with Open CPX.

• No standard for detachable fiber arrays: asked about detachable FAUs, Hutchins said OIF has not started on it and wants the industry to find what works first.

• The numbers are targets, not measurements: under 7 pJ/bit assumes 200G and half-retimed operation; the pod power chart is a hypothetical configuration.

• Terminology is still in conflict: OIF itself notes that some NPO-HDI implementations are called "CPO", which will keep confusing procurement and spec discussions.

7. What It Means for Taiwan's Supply Chain

• An open footprint is the entry ticket for module makers. The 12.8T NPO explicitly aims for a defined pin map and multi-sourcing; once the IA is final, module makers and assemblers can build to the standard instead of a single ASIC vendor's proprietary design. Taiwanese contract manufacturers and assemblers should watch when the IA draft opens for member review.

• Liquid cooling moves from a system problem to a module spec. Kocsis noted it is still unsettled whether the system builder or the module maker owns thermal management; once a liquid-cooling thermal interface is written into the module spec, the interface for cold plates and liquid-cooling parts gets standardized. Taiwan is a major source of cold plates and liquid-cooling components, so this spec-level change is worth tracking.

• Laser source provisions extend ELSFP. The 12.8T NPO scope includes laser source provisions, and OIF already has the ELSFP implementation agreement. Demand for external CW lasers would grow with NPO, but the talk did not say whether integrated or external lasers will be used.

• BiDi and EBO connectors reshape fiber and connector demand. Half the fibers and expanded-beam connectors moving up mean a product-mix shift for MPO and fiber jumper makers, not simply more volume.

8. Summary

The talk had no headline-grabbing new numbers, but it answered the question left by the requirements document two years ago: OIF's answer is not CPO but NPO plus RTLR. Under 7 pJ/bit and over 1 Tb/s/mm is a compromise between pluggables and CPO that can be multi-sourced and serviced.

The bigger signal is that the bottleneck has moved. Density discussions used to focus on connectors and shoreline; OIF's own framework shows that at 2D density even 5 pJ/bit exceeds air cooling, so a 12.8T NPO has to be liquid cooled. Three things to watch over the next 12 months: when the 12.8T NPO implementation agreement is finalized, whether 224G RTLR arrives in time for the 200G/lane volume window, and whether OIF fills the gaps on cooling and detachable fiber arrays.

Whether a standards body can keep pace with AI depends not on pJ/bit, but on when the 12.8T NPO moves from "in progress" to "published".

This article is for technology and industry trend analysis only and does not constitute investment advice.