OCP Global Summit 2026 | Eridu, Delos Data | Promode Nedungadi, Dan Daly | Breaking up the Monolith

3 minutes ago

7 min read

1. Two startups take on the monolithic rack

The talk was given by two CTOs: Dan Daly, CTO and co-founder of Delos Data, covered the architecture and data-hall layout; Promode Nedungadi, CTO of Eridu, covered how the switch would be built. The cover slide carries the OCP Startup Member badge. Eridu builds high-radix Ethernet switching systems with a public goal of single-hop domains of thousands of GPUs, but has disclosed neither chip specs nor a timeline. This was not a product launch; it was a requirements document for that switch.

Daly opened with a jab at the expo floor: some of the rack-scale systems on show were too heavy to bring into the venue and appeared only on screens, drew too much power to switch on, and a single rack is now approaching 1 MW. The slide lists the problems of the monolithic rack plainly:

Extreme power density (MW-class per rack), heavy and hard to service
A practical limit of about 64 GPUs, plus 8 spares
Workloads must be packed into 64-GPU bins, so placement is inefficient
Closed, single-vendor architectures

The monolith's one irreplaceable strength is a single hop: any two GPUs in the rack cross only one layer of switching, giving low latency and little congestion. Daly's position: if you break up the rack, you must keep the single hop; and it must be open, because "if it's not open, it's just a bigger monolith."

The demand pressure comes from MoE. Routed experts per model cited on the slide go from 128 in Llama 4, 256 in DeepSeek-V3 and 384 in Kimi K2 to 896 in Kimi K3, with 2,000 to 5,000 projected for 2028–29; over the same period, peak FLOPs per package reach 49x the 2023 level by 2028. Every wait for experts to return results is, in the speaker's words, "venting heat into space."

2. Unpacking the nominal numbers: an 8x to 128x gap

System	Announced scale-up domain	Single-hop domain	Gap (STT calculation)
NVIDIA NVL72 / AMD Helios	72	72	1x
NVIDIA NVL576 (2027)	576	72	8x
NVIDIA NVL1152 (2028)	1,152	144	8x
OpenAI Jalapeño	2,048	128	16x
Microsoft Maia 200	6,144	48	128x

▲ Announced scale-up domains and the actual single-hop domains differ by 8x to 128x, while all 5,120 endpoints in Eridu's proposal are single-hop (Image source: Simple Tech Trend original; data from Eridu and Delos Data 2026 OCP Global Summit presentation)

The slide lists four issues: closed architectures; nominally large domains are built from smaller single-hop domains; rack-to-rack performance is lower than in-rack, sometimes significantly; and topology-aware job placement is still required inside the scale-up domain.

Most of today's "thousand-GPU scale-up" domains are several islands of 72 or 144 GPUs stitched together by a second switching tier. For anyone running MoE inference, the hop between islands is where the latency comes from.

3. Unpacking the data hall: 5,120 endpoints, longest run only 30 m

Daly's approach takes the in-rack "multi-plane, single-hop" design and spreads it unchanged across many racks. Three building blocks:

Servers with optical scale-up: all GPU scale-up interfaces are brought out to the front panel, with no internal interconnect, so the server "looks like a switch"
Optical MSAs: OCI, for example, takes links beyond the few meters copper can reach; we covered this spec in Meta, Broadcom and AMD define the OCI 200G line-side spec
High-radix, low-latency switches: open Ethernet compliant with UEC and ESUN

Compute racks and switch racks are separated, and every GPU-to-GPU path is "out of the rack, into a switch rack, one hop, and back," so all devices are roughly equidistant. The slides give three layouts (racks 21 in x 36 in x 42 OU, 7 ft row pitch):

Endpoints	Rows	Compute / switch racks	Longest cable run
128	1	4 / 1	~3.7 m
2,048	5	50 / 10	~15 m
5,120	12	120 / 24	~30 m

▲ A 5,120-endpoint layout across 12 rows of racks, with the longest fiber path about 98 ft (about 30 m), from rack 1 in row 1 to the switch rack in row 12 (Image source: Eridu, Delos Data | 2026 OCP Global Summit presentation)

Two numbers stand out. First, each compute rack holds only about 41 to 43 endpoints on average (STT calculation: 2,048 ÷ 50 ≈ 41, 5,120 ÷ 120 ≈ 43), and the 128-endpoint version only 32, far below the monolith's density. Breaking up the rack buys lower power density, with no need to cram 1 MW into one rack. Second, light propagation over 30 m is about 150 ns (STT estimate at roughly 5 ns per meter), which the speakers called "negligible."

4. Unpacking the switch: 5,120 ports is 1 Pb/s

Daly noted that switches with 512 ports are already on the market, enough to build a 512-endpoint single-hop cluster; 2,000 endpoints "only" needs a switch of radix 2,000. It sounds casual, but plugging in a port speed shows the scale (STT calculation, assuming 200G per port):

102.4T ÷ 200G = 512 ports, exactly today's ceiling
2,048 ports x 200G = 409.6 Tb/s
5,120 ports x 200G = 1.024 Pb/s

▲ Growing a single-hop domain from 512 to 5,120 endpoints only stretches cable length from about 10 m to 30 m, but switch capacity has to rise from 102.4T to about 1 Pb/s (Image source: Simple Tech Trend original; data from Eridu and Delos Data 2026 OCP Global Summit presentation)

When Nedungadi took over, he drew this line using 650 Group's volume-shipment years:

51.2T (2022): monolithic ASIC, embedded I/O, 5 nm
102.4T (2026): monolithic core, separate I/O tiles, 3 nm
Next: 10x, petabit-class

▲ Switch silicon took 4 years to double from 51.2T to 102.4T; petabit class needs a 10x jump in one step (Image source: Eridu, Delos Data | 2026 OCP Global Summit presentation)

His argument: the last generation only split I/O into chiplets and lengthened the die shoreline, while the switching core stayed monolithic; a 10x jump requires redesigning the core itself. Four directions: a larger silicon canvas (advanced packaging), distributed buffering that behaves like a single core, I/O flexible enough for pluggables, OpenCPX, CPO, NPO and even VCSEL and microLED, and 100% liquid cooling plus power delivery.

In time terms (STT calculation): the last 4 years delivered 2x; 10x takes about 3.3 doublings. At that pace it would take more than a decade; even at a two-year doubling it lands around 2032. That is why Eridu calls for a "revolution," and it is the biggest schedule variable in this architecture.

5. Unpacking the payoff: GPU utilization from 64% to 88%

The last data slide cites a third-party simulation (a training simulation by Turbalance for HotInterconnects 2026). Per the speaker's verbal description (not on the slide), the scenario extrapolates a Llama 4 Maverick-based model to 2028, about 20 trillion parameters and about 2,300 GPUs: GPU utilization is 64% with a 230T switch and 88% with a petabit switch, a relative gain of 38% (88 ÷ 64 ≈ 1.375).

▲ Third-party training simulation: GPU utilization is 64% with a 230T switch and 88% with a petabit switch, a 38% relative gain (Image source: Eridu, Delos Data | 2026 OCP Global Summit presentation)

The talk closed with a new OCP workstream, Open Multi-rack Scale-up Domains: a reference architecture that scales from hundreds to thousands of endpoints, built on four principles: multi-rack single-hop, disaggregated mix-and-match compute and networking, heterogeneous compute (GPUs, CPUs, xPUs), and open standards (ESUN, ORv3, OCI). The whitepaper is available on request and the kickoff is set for early November. This echoes what we saw in Ethernet starts eating scale-up: control of the scale-up spec is moving from a single vendor toward the open Ethernet camp.

6. Risks and counterarguments

The petabit switch does not exist yet. The most critical component in the whole talk has only a design direction, with no chip specs, power or schedule. The 5,120-endpoint layout rests on a switch that has not been disclosed.
The 38% is a simulation, and the baseline is 230T. 230T is already more than twice today's 102.4T, and the simulation did not use a multi-hop architecture such as NVL576 as a control, so the real-world gain is unverified.
Fiber density in the switch racks is a new challenge (STT estimate; the deck gives no per-xPU scale-up bandwidth). Assuming 14.4 Tb/s per direction per xPU (roughly NVLink 6 class, as an order of magnitude only) at 200G per port, you need 72 planes, i.e. 72 switches of 5,120 ports, 3 per switch rack; that is about 369k links system-wide, about 740k fibers at one fiber pair per link without WDM, or about 30k fibers per switch rack. Fiber count is exactly what stopped the slow-and-wide approach before; see What killed slow-and-wide wasn't physics, it was 60,000 fibers (in Chinese).
Optical reliability directly determines the value of single-hop. Every GPU pair is separated by two optical links, any link flap affects the whole domain, and the deck gave no reliability data.
Disaggregation dilutes density. Around 40 endpoints per rack means the same compute takes more floor space and more racks.

7. What it means for Taiwan's supply chain

Server and rack design will change. The compute servers described have no internal interconnect, bring all scale-up interfaces to the front panel and put switching in a separate rack, with ORv3 named as one of the open principles. Taiwanese ODMs are major manufacturers of OCP racks, so high-density front-panel optical connectivity and the integration of switch racks and patch panels become new design problems; at the same summit, Wiwynn gave a separate talk on optical scale-up with CPO on open rack-scale infrastructure, worth reading alongside this one.
Switch packaging is the second entry point. Eridu said plainly that a petabit switch needs a "larger silicon canvas," meaning advanced packaging and 100% liquid cooling. Large-format advanced packaging capacity today sits mainly with TSMC, but Eridu named no foundry or packaging partner, so we draw no conclusion here.
On the module side, MSAs such as OCI remain the core. If the workstream kicking off in November writes OCI into the reference architecture, the supply-chain opportunity is short-reach optics within 30 m across racks, not longer-reach modules.

8. Conclusion

The real contribution of this talk is that it changes the unit for "how big is scale-up": ignore the announced domain and count only the single-hop domain. By that measure, every system announced through 2028 still sits at 48 to 144 GPUs single-hop.

Eridu and Delos Data were also candid that optical reach is no longer the problem; the problem is that switch radix must jump 10x at once. That moves the main battlefield of scale-up from optical modules and copper to switch silicon architecture and packaging. Three things to watch over the next 12 months: when Eridu discloses its switch specs, whether the workstream whitepaper's reference architecture adopts OCI and ESUN, and whether next-generation NVIDIA and Broadcom products push the single-hop domain past 144.

Whoever makes a single-hop domain of thousands of GPUs owns the definition of scale-up; until that petabit switch ships, every thousand-GPU domain is just a set of islands.

This article is for technology and industry trend analysis only and does not constitute investment advice.