OCP Global Summit 2026 | Wiwynn, Ayar Labs | Kinny Chen, Vishal Chandrasekar | Open Rack-Scale Optical Infrastructure for AI Scale-Up with CPO

1. Why Wiwynn and Ayar Labs shared the stage

Ayar Labs builds optical engines and external lasers; Wiwynn builds the racks and trays. The two were blunt about the division of labor: Ayar Labs' Vishal Chandrasekar said customers usually reply, "Your technology is great, now show me you can deploy it in a gigawatt-scale data center." This talk is that proof.

The motivation comes from the first chart: the y-axis is token throughput per 100 MW, the x-axis is tokens per second delivered to a single user. With a 64-GPU scale-up domain, the two generational curves almost overlap and interactivity stays below roughly 40 tokens per second; the 1024-GPU CPO curve extends out to about 320. The slide's conclusion: a 1024-ASIC pod is projected to deliver about 10x the system performance of the smallest evaluated configuration (32 GPUs), with communication-bound workloads benefiting most.

The problem is that 1024 ASICs do not fit in one rack. Chandrasekar put a GPU at about 3 kW, so the ASICs alone come to about 3 MW (STT estimate); and scale-up bandwidth per ASIC has to keep rising, which copper cannot carry. Both reasons point to the same answer: optics must span racks and sit as close to the ASIC as possible. The unit of compute moves from GPU to chassis to rack, and next to "a row."

2. Layer one: from vertical copper to horizontal optics

Today's in-rack scaling sandwiches switch trays between compute trays and links them vertically with copper. Wiwynn's design turns the connections "from vertical to horizontal": compute racks and scale-up switch racks are separated and linked sideways with fiber.

The topology deliberately stays single-stage: ASIC → Switch → ASIC, the same as today. The cost lands on the switch: each scale-up switch must handle 1024 bidirectional signals, with the same optical I/O spec as the compute side. In other words, the switch side needs optical I/O matching the compute spec; STT reads this as the switch also having to go CPO or an equally dense optical PHY.

Stringing the slide numbers together, the pod looks like this:

Level	Count	Source
ASICs per tray	2 (sharing 1 CPU)	Slide 6, spoken
Trays per compute rack	32 x 1OU	Slide 5
ASICs per compute rack	64	STT estimate
Compute racks for 1024 ASICs	16	STT estimate
Scale-up bandwidth per ASIC	200+ Tbps	Slide 7
Scale-up bandwidth per compute rack	≥ 12.8 Pb/s	STT estimate

▲ A 1024-ASIC pod breaks down into 16 compute racks, 32 trays per rack, and 2 ASICs plus 16 ELSFPs per tray, with at least 12.8 Pb/s of scale-up bandwidth per rack (Image source: Simple Tech Trend original, data from Wiwynn, Ayar Labs 2026 OCP Global Summit presentation)

3. Layer two: the shuffle box is the joint of the whole architecture

Layer two is fiber routing. There are four rules: every ASIC connects to every scale-up switch; all ASIC scale-up fibers first land in the in-rack shuffle box; each compute rack has at least one fiber pair to each switch rack; and each switch rack also holds 32 x 1OU trays plus a shuffle bus.

Wiwynn uses the ORV3 rack as its reference. Each tray's optical I/O goes to a patch panel first (the slide lists MPO, MMC and EBO interfaces), then into the shuffle box, which distributes each compute tray's fibers across the switch racks.

▲ The shuffle box in each compute rack fans out the fibers from all 32 trays and connects them to every scale-up switch rack (Image source: Wiwynn, Ayar Labs | 2026 OCP Global Summit presentation (p. 5))

The point of this design: the all-to-all complexity is folded into one box inside the rack. Between racks there is only structured cabling, which field crews can install from a table. As we argued in It Is Not Physics That Kills Slow-and-Wide, It Is 60,000 Fibers (in Chinese), fiber count is the real bottleneck for scale-up optics; the shuffle box is the system builder's engineering answer.

4. Layer three: what fits inside a 46.5 mm tray

The L10 tray measures 805 x 537 x 46.5 mm. Kinny Chen said that this height has to hold liquid cooling, fiber management and ever-larger ASICs, while keeping the bend radius of every fiber from each optical I/O to the front panel.

The tray contains: cold plates and an inner manifold, fiber cables and guiding parts, 2 CPO ASIC boards, a CPU board in the middle, DC-SCM and its interposer, an OCP 3.0 NIC for scale-out, a 12V-to-3.3V power board, and on the front panel an ELSFP board with 16 ELSFPs. A tray has 16 optical engines (2 x 8), matching the 16 ELSFPs one-to-one in count (STT estimate; the slides do not state the mapping).

▲ The L10 tray measures 805 × 537 × 46.5 mm and integrates 2 CPO ASIC boards, a CPU, DC-SCM, an OCP 3.0 NIC and 16 front-panel ELSFPs (Image source: Wiwynn, Ayar Labs | 2026 OCP Global Summit presentation (p. 6))

This is where the slide's five design considerations come from:

• Two thermal domains: ASIC and optical engine heat versus the ELSFP laser temperature window.

• Front-panel consumable: ELSFPs must stay hot-pluggable and reachable, with space reserved for NIC, SSD and BMC.

• Fiber as structure: bend radius, polarization-maintaining (PM) fiber orientation, service loops.

• Fragmented power tree: 48V / ±400V / 800V comes in at the rear, while the front panel needs 3.3V.

• Cross-supplier test boundary: optical loss can originate at multiple points owned by different suppliers.

▲ From the compute tray, chassis fiber bundles, patch panel and CPO switch rack to data hall structured cabling, plus five design considerations (Image source: Wiwynn, Ayar Labs | 2026 OCP Global Summit presentation (p. 3))

In STT's view, the first four have established engineering methods; the fifth does not. An optical path runs from the optical engine through a detachable connector, the in-chassis harness, the patch panel and the shuffle box to the switch, and each segment may belong to a different supplier. When loss is out of spec, who is responsible? The talk lists "deployment and validation practices" as a call to action, which signals the industry has no common method yet for measurement and accountability.

5. Layer four: package and thermals, the optical engine is no longer the weakest link

The package was built by Ayar Labs with Alchip: two AI dies in the center, HBM on the east and west sides, I/O dies on the north and south; 8 optical engines sit on the substrate, not on the advanced-package interposer. Chandrasekar said verbally that the optical engines are based on TSMC's COUPE platform (the ASR transcript reads "Co-Op"; STT reads it as COUPE; the slides do not name it). They use a microring architecture with an OCI MSA optical PHY and connect to the I/O dies over UCIe-S, with the I/O dies converting UCIe-A to UCIe-S. Each accelerator gets 200+ Tbps of scale-up bandwidth, which Chandrasekar called about an order of magnitude more than today's state-of-the-art accelerators. The optical connectors are detachable, so fibers are attached as the last step of tray assembly. A similar package was built with GUC.

For background on OCI MSA, see Meta, Broadcom and AMD Define the OCI 200G Line-Side Spec.

Thermals are the most common objection to microrings. The simulation assumed 25°C ambient and a TIM conductivity of 5.2 W/mK, with impingement cold plates on both the ASIC and the optical engines, each at 4.5 LPM:

Component	Spec Tj	Simulated Tj-max	Margin (STT calc)
SoC	125°C	112°C	13°C
HBM4	95°C	75.4°C	19.6°C
I/O die	125°C	59.9°C	65.1°C
Optical engine	100°C	69.8°C	30.2°C

▲ With a 4.5 LPM impingement cold plate, the optical engine has 30.2°C of margin while the SoC has only 13°C; the optical engine cold plate's pressure drop is 18.8 kPa, about 68% higher than the ASIC cold plate (Image source: Simple Tech Trend original, data from Wiwynn, Ayar Labs 2026 OCP Global Summit presentation)

One detail is worth noting: the optical engine cold plate's pressure drop is 18.8 kPa versus 11.2 kPa for the ASIC cold plate, about 68% higher at the same flow (STT calc). The optical engines run cool, but their cold plates are harder to push water through; scaled to a full rack, that may eat into CDU pump headroom (STT inference).

6. Risks and counterarguments

• The thermal data is simulated: the slide is literally titled "Package Thermal Simulation." The 69.8°C figure assumes 25°C ambient and an ideal TIM; real inlet temperatures and TIM aging will erode the margin.

• The switch side is not explained at all: who supplies a switch with 1024 bidirectional signals at the same optical I/O spec, and when, was not addressed, nor was the number of switch racks. This is the precondition for the whole pod.

• The bandwidth claim is a verbal comparison: "an order of magnitude more than current accelerators" names no comparison point, and 200+ Tbps comes without lane count or per-lane rate.

• The cross-supplier test boundary is only a stated problem: the call to action lists a common physical interface, deployment and validation practices, system telemetry and a reference rack design, but these are still agenda items with no timeline.

• A closed solution may arrive first: if a major GPU vendor ships its own full-rack solution, an open reference rack becomes the second choice. For the trade-offs among scale-up paths, see After Copper Runs Out: Seven Paths for Scale-Up Optical Interconnect.

7. What it means for Taiwan's supply chain

• Wiwynn is the system definer of this architecture. The L10 tray, shuffle box and patch panel layout are its designs, built on OCP's ORV3 rack, and a working CPO tray was shown at booth C74. STT's view is that as scale-up becomes a row-of-racks engineering job, the ODM role moves from "assembly" toward "defining the optical path and the validation boundary," a higher-value position.

• Alchip and GUC are the ASIC-side partners. Both were named verbally by Ayar Labs during the talk (not on the slides), showing CPO packaging has entered the project scope of ASIC design-service houses, not just switch-chip vendors.

• TSMC COUPE is the optical engine platform. According to what was said in the talk, Ayar Labs' optical engines are based on COUPE, so this CPO's volume ramp is tied to the progress of TSMC's silicon photonics platform.

• Taiwanese suppliers should prioritize the cross-supplier test boundary. Whoever proposes an adoptable method for optical-loss measurement and accountability will win a position in the reference rack specification.

8. Summary

This sub-14-minute talk moved the CPO debate from "will the optical engine run too hot" to "how do you wire a row of racks." The chip-side answer is in: the optical engine has 30°C of margin, more than the SoC. The remaining challenges are all at the system level: matching optical I/O on the switch side, all-to-all routing through the shuffle box, fiber bend radius inside a 46.5 mm tray, and cross-supplier optical loss with no clear owner.

STT's view: the 2027-2028 volume bottleneck for CPO scale-up is not the optical engine but rack-level test and validation. Three indicators to watch: whether OCP publishes a reference rack spec for short-reach scale-up optics, whether that spec adopts Wiwynn's shuffle box and patch panel design, and when a switch with 1024 bidirectional optical I/O is disclosed.

The optical engine has proven it can take the heat; what remains to be proven is that every segment of fiber from chip to switch has an owner.

This article is for technology and industry trend analysis only and does not constitute investment advice.