OCP Global Summit 2026 | OIF | Nathan Tracy, Yi Tang, Cathy Liu | Defining Electrical 448G/Lane

1. Why This Session Matters: OIF's Electrical Specs End Up in IEEE and InfiniBand

OIF's CEI (Common Electrical I/O) is not a niche specification. Nathan Tracy of TE Connectivity, OIF President, opened by laying out the history: from 0.8 Gbps in 2000 to 224 Gbps today, IEEE, InfiniBand, Fibre Channel, Interlaken and ITU have all adopted or drawn on CEI's electrical definitions.

Spec	Rate per pair	Year
CEI-28G	28 Gbps	2012
CEI-56G	56 Gbps	2017
CEI-112G	112 Gbps	2024
CEI-224G	224 Gbps	2026?

OIF uses the same playbook every generation: publish a framework white paper so the industry shares one language, then split the work into electrical interfaces by reach. At 224G there were five classes: XSR (50 mm package substrate), VSR (200 mm host plus 20 mm module, one connector), MR (500 mm, one connector), LR (1,000 mm of host and daughter cards, two connectors), and Linear, which needs no DSP in the module.

In ECOC2026 | Three Hours of Fast-Narrow vs Slow-Wide: 448G Is the Dividing Line we argued that 448G decides whether the fast-and-narrow path can continue. This OIF workshop answers a more basic question: can the 448G electrical interface be defined at all.

2. Timeline Breakdown: VSR and LR First, Other Variants Follow

OIF's 448G timeline:

• August 2024: CEI-448G framework project started

• November 6, 2025: framework document OIF-FD-CEI-448G-01.0 published

• February 2026: CEI-448G-VSR and CEI-448G-LR projects started

The framework lists seven potential applications: die-to-die in a package (about 25 mm), die to optical engine in a package (about 50 mm), chip to nearby optical engine (about 150 mm, the NPO case), chip to pluggable module (about 250 mm), chip to chip within a PCBA (about 50 cm), and across a backplane or between chassis (about 1 m).

OIF opened only two projects, and the positioning is blunt: VSR is "compatibility with optics", LR is "pushing the limits of copper", with a note that VSR/LR power and cost reduction will drive the other variants. In other words, XSR, the short-reach interface for NPO, and Linear all wait for these two backbones.

▲ OIF uses the 224G roadmap as its template; the first 448G wave opens only two projects, CEI-448G-VSR and CEI-448G-LR (Image source: OIF | 2026 OCP Global Summit presentation (13:18))

After the talk, Bob Wheeler of LightCounting asked whether OIF had considered interim options already in the market, such as 224G simultaneous bidirectional signaling or 300G per lane. Tracy said OIF did not see industry-wide demand and is staying with the traditional doubling. That tells the market interim solutions will remain proprietary choices, not standards.

3. Channel Breakdown: Where the Margin Goes

Yi Tang of Cisco (OIF board member and PLL Working Group Electrical Vice Chair) took the question of where channel margin goes. Using representative 224G VSR BGA-to-BGA channel models, he showed that the channels behave reasonably around 56 GHz, roll off quickly with resonances beyond about 80 GHz, and are no longer a smooth extension by 100 GHz.

▲ 448G PAM6 and PAM4 Nyquist frequencies against connector bandwidth progress: compression-mount and CPC connectors already clear the PAM6 target, while PAM4 still needs 112 GHz of bandwidth (Image source: Simple Tech Trend; data from OIF's 2026 OCP Global Summit presentation)

Overlay 448G and the problem is clear:

Modulation	Baud rate	Nyquist frequency
224G-PAM4	112 GBd	56 GHz
448G-PAM8	about 149 GBd	about 75 GHz
448G-PAM6	about 179 GBd	about 87-89 GHz
448G-PAM4	about 212 GBd	106-112 GHz

The PAM6 target lands right in the roll-off region of today's channels, and PAM4 lies beyond the measured data. OIF's conclusion: a 224G channel will not simply grow into a 448G channel; connectors, transitions, packages, PCBs and cables all need rework.

Tang named three factors that were minor in earlier generations but become major challenges at 448G:

• Transitions: ASIC escape, package to CPC, cable to module; every transition brings impedance discontinuity and multiple reflections. With shorter UIs, reflections are harder to tolerate, and margin depends on the whole interconnect rather than loss per inch

• Crosstalk and reflections rise with frequency: attenuation is familiar, but crosstalk and reflections both rise at high frequency, squeezing usable bandwidth from both sides

• Intra-pair skew: twinax skew varies with frequency, causing jitter and differential-to-common-mode conversion. OIF thinks new specification parameters may be needed; this is still under study

4. Connector Breakdown: Timing Decides Modulation

This is the most important slide for the supply chain. The OIF framework summarizes connector bandwidth progress:

• OSFP Gen2-Rev1: usable bandwidth about 67 GHz, below both the PAM4 and PAM6 targets for 448G

• OSFP Gen2-Rev2: raised to about 85 GHz, still below the PAM6 target

• Compression connectors (late 2024): toward 100 GHz, with useful bandwidth for PAM6

• Emerging CPC interconnect (2025): insertion and return loss performance beyond 106 GHz, giving margin for PAM6 and advancing toward the PAM4 target

▲ Connector bandwidth progress compiled in the OIF framework document: OSFP Gen2 at about 67–85 GHz, compression-mount near 100 GHz, and CPC above 106 GHz (Image source: OIF | 2026 OCP Global Summit presentation (22:46))

OIF chose its words carefully: continued connector advances are expected to make 448G PAM4 feasible, but their timing could strongly influence the standardization approach for each interface. In plain terms: if connectors cannot clear 112 GHz before 2027, VSR may well be pushed to PAM6.

CPC is attractive because it attaches the high-speed cable at the package and bypasses the package-to-PCB BGA escape, the hardest part to control at 448G. But Tang also kept the door open for PCB: in representative 224G data, PCB traces show less skew variation than twinax; PCB manufacturing is mature and low cost; narrower BGA pitch and better transition geometry reduce parasitics, and better materials and process control may push usable bandwidth toward 448G.

5. SerDes Breakdown: Only Modulation and Inner FEC Left in the Toolbox

Cathy Liu of Broadcom summarized twenty years of SerDes evolution in one table:

Rate per lane	Modulation	Nominal cable reach	Technology added	Year
11G	NRZ	7 m	DFE	2007
28G	NRZ	5 m	RS FEC	2014
56G	PAM4	3 m	Stronger RS FEC	2018
112G	PAM4	2 m	Floating tap DFE	2022
224G	PAM4	1-2 m	MLSE	2026 (estimated)
448G	PAM4, PAM6?	1 m	Inner FEC?	ASAP

Each doubling of rate shortens copper reach, and at 448G the nominal reach is just 1 meter. Her view is that DSP equalization (FFE/DFE/MLSE) alone is no longer enough, leaving two pivotal tools: modulation and inner FEC.

▲ Broadcom breaks down 448G modulation by topology: passive-copper LR leans toward PAM6, VSR is under evaluation, and LPO/LRO must be PAM4 (Image source: OIF | 2026 OCP Global Summit presentation (35:26))

Modulation is decided per topology:

• LR (passive DAC and backplane): the channel is near its physical limit, so PAM6 is a good starting point and may stay the primary choice for a long time. PAM4 over longer reach will depend on active copper such as AEC/ACC

• VSR (chip to module): everyone hopes for PAM4 because it matches 400G optical lanes, but a careful study must prove PAM4 meets reach and yield in high-volume deployment. Alternatively, PAM6 on the host with a lightweight 6-to-4 gearbox in the module gives one SerDes mode for passive copper, active copper and retimed optics

• LPO/LRO: with no DSP in the module to clean up the signal, PAM4 is mandatory and the host channel loss budget must shrink. NPO and CPO make this viable by moving the optical engine close to the host die

PAM6 is not free. It carries about a 3.6 dB SNR penalty versus PAM4, which inner FEC must recover; but adding FEC means raising the baud rate. Liu's numbers: going from 165 GBd to 180 GBd costs about 0.4 dB of net coding gain on an ideal channel but 1.8 dB on a long-reach channel, almost wiping out the coding gain that was added. So OIF favors net coding gain as the metric and simple short codes (t=1 or t=2), with the inner code sitting next to the SerDes DSP; the PHY and FEC can no longer be specified separately.

6. Risks and Counterarguments

• Dual-mode SerDes is not cheap: asked whether one SerDes can support both PAM4 and PAM6, Liu said "not that easy", and two separate developments may be needed. That adds cost for IP and chip vendors and may fragment the market.

• PAM6 makes optics more expensive: optics have long been PAM4, so a PAM6 host needs a gearbox in the module. Liu calls it lightweight and low cost, but it only works for retimed optics and is incompatible with the LPO path.

• Proprietary interim solutions may move first: OIF is not pursuing 300G per lane or simultaneous bidirectional 224G, but platforms with urgent needs may not wait for the standard.

• Connector timing is the biggest variable: OIF itself admits connector timing affects the standardization approach; if CPC volume production slips, the VSR modulation decision may be delayed.

• Standards set direction, not pace: in OIF Draws the Official Map for AI Interconnect OIF laid out energy-efficiency requirements for AI interconnect, but when 448G ships is ultimately set by hyperscaler and chip-vendor platform schedules.

7. What It Means for Taiwan's Supply Chain

• High-speed PCB and CCL materials will not be displaced by CPC, but the bar rises again. OIF says PCB is still worth pursuing for cost and maturity, but reaching 448G needs narrower BGA pitch, better transition geometry and better material control. For Taiwan's AI server and switch board makers and high-speed CCL suppliers, this is a spec upgrade, not lost demand.

• Connector bandwidth is this generation's key bottleneck. The bandwidth curves on the slide (OSFP Gen2, compression, CPC) decide whether VSR goes PAM4 or PAM6. Taiwanese connector makers aiming at 448G need data on bandwidth and measurement capability above 100 GHz.

• OIF formally writes active copper (AEC/ACC) into the roadmap. If LR runs PAM4 over longer reach, it needs active copper; this continues the trend we tracked in Earnings Highlights: Amphenol (APH) | Q2 FY2026, and extends the product line for Taiwan's cable assemblers.

• A twinax skew specification may be added. OIF says cable suppliers must control frequency-dependent intra-pair skew; once specified, wire makers' measurement and process capability becomes a qualification gate.

8. Conclusion

The key message from this OIF workshop is that 448G no longer has one modulation for everything. LR leans PAM6, LPO is locked to PAM4, VSR is undecided, and what decides VSR is not SerDes design but whether connector bandwidth can clear 112 GHz in time.

On timing, the VSR and LR projects only started in February 2026, so watch for the specification to land after 2027. Over the next 12 months, watch three things: the VSR PAM4 feasibility conclusion, volume-production bandwidth of CPC and next-generation OSFP connectors, and the inner FEC architecture choice.

448G will be won not by how fast the SerDes runs, but by how far connectors and PCBs let the signal travel.

This article is for technology and industry trend analysis only and does not constitute investment advice.