The 400G-per-lane era is here. At OFC 2026, Coherent showed InP components with more than 100 GHz of bandwidth - but how do you keep TDECQ low while absorbing a 5 dB sensitivity penalty? A deep dive into the technical and commercial tradeoffs of IM/DD for AI interconnects.

AI compute demand is forcing Ethernet to evolve faster than ever, and OFC 2026 marked the official start of 400G-per-lane work. Experts from Meta, Cisco, Synopsys and Dell'Oro explain how 1.6T and 3.2T networks will scale under hard power and space limits.

Silicon photonics gets the spotlight, but Intel's 0.9 pJ/b 108G PAM4 link shows VCSELs remain an underrated low-power path for short-reach CPO. We walk through this CICC 2026 paper section by section, figure by figure, and identify the last three miles VCSEL CPO must cover to reach volume: equalization, packaging and thermals.

Marvell's 3nm FinFET 212.5Gbps SerDes hits 54.7dB reach and 2.05pJ/bit, the longest-reach and most efficient published at this rate. A shared PLL plus heavy DSP equalization breaks the old rule that reach costs power, giving 1.6T racks structurally more room in cable length and power budget.

AI compute is ushering in the 3.2T optical era. We break down Mitsubishi Electric's latest paper: a 0.8 µm high-mesa EML, a Glass-AlN hybrid substrate, and wire-bond-free packaging that push modulation bandwidth past 100 GHz for next-gen CPO and GPU clusters.

Jensen Huang declared that "compute has been disaggregated"; Matt Murphy supplied the missing physical timeline. AI's next bottleneck is connectivity, and the deciding factor is a copper wall moving into the rack. Every doubling of bandwidth halves copper reach — at 400G/lane, copper can't even span a single rack, and physics forces CPO from slideware into shipments.

Broadcom's latest 200G VCSEL paper reports over 35 GHz bandwidth and about 1 pJ/bit efficiency, paired with a new NPO architecture aimed at replacing copper in AI scale-up networks. We walk through all 12 figures.

17, 25, 30, 38, 72 fs: at least two things about these six 312.5 MHz-class clock datasheets can mislead you. After the receiver equalizer, their TDECQ is nearly identical. The real clock bottleneck only hits at 448G/lane.