OFC 2026 - Ethernet's Accelerating Evolution for AI: 400G per Lane and the Road to 6.4T - Meta, Cisco, Synopsys, Dell

2 days ago

3 min read

On the OFC 2026 stage, an expert panel led by the Ethernet Alliance sent a clear signal: growth in AI compute demand has entered a "crazy" phase, and it is forcing Ethernet to evolve faster than ever before. As single-lane rates officially head toward 400G per lane, the supply chain faces a triple test of physical limits, power challenges and supply bottlenecks.

The session not only laid out the foundational architecture for 1.6T and 3.2T Ethernet, but also showed how hyperscalers are redefining the physical-layer requirements of the AI fabric across three dimensions: scale-up, scale-out and scale-across.

Core Technologies and What Each Company Said

Meta (Halil Cirit): Physical Limits and the Analog Design Dilemma

Speaking as an end user, Meta stressed that data center infrastructure has reached a tipping point.

Physical space and power limits: Rack weight, cooling capacity and power delivery have all hit their ceilings, so capacity can no longer be added simply by making things bigger.
The analog design dilemma: Compute chips chase leading-edge nodes (3nm/2nm), but SerDes analog designers dislike the noise those nodes bring and prefer to stay a few generations behind.
The urgency of a 400G electrical interface: Meta wants to double compute and memory bandwidth without replacing the rack system, which makes 400G per lane the only option.
The need for open standards: Meta argues for releasing specs early so suppliers have enough time to prepare, as a counterweight to closed systems.

Cisco (Mark Nowell): A Three-Tier Network Architecture and Copper's Last Line of Defense

Cisco presented a visual model of AI infrastructure that divides the network into three scenarios:

Scale-up (GPU-to-GPU): Very short reach inside the rack, high density and ultra-low latency. Today "Copper is King," but 400G will put it under enormous strain.
Scale-out (Rack-to-Rack): Rack-to-rack traffic is dominated by optics today and will shift from pluggables to CPO (Co-Packaged Optics).
Scale-across (Building-to-Building): Once AI clusters outgrow a single data center, links must span buildings (up to 3km), bringing in coherent optics and deep-buffer switch silicon.

Synopsys (Kent Lusted): The IEEE 400G Study Group Toolbox

Kent announced that IEEE formally approved a 400 Gb/s per lane Study Group the previous week, focused on electrical interconnects and 500m single-mode fiber.

Technology paths under study: Including the PAM4 vs. PAM6 modulation choice, advanced DSP, and lower-loss packaging materials.
A more diverse FEC (forward error correction) menu: To balance latency and performance, IEEE is considering a "menu" of FEC options, including end-to-end, concatenated and segmented FEC.
Architectural flexibility: Support for multiple architectures, including linear (LPO), half-retimed and fully retimed.

Dell’Oro Group (Sameh Boujelbene): Supply-Driven Standardization

Market analysis shows that today's AI networking market is shaped by supply, not demand.

Vendor diversity: To spread TSMC capacity risk, hyperscalers must source switch silicon from multiple vendors, which directly drives demand for interoperability and standardization.
Projected timeline: 3.2T interfaces are expected to appear in 2029-2030, while 6.4T interfaces could arrive around 2034.

Where the Panel Agreed and Where It Split

Consensus: Standardization Must Move Faster

All speakers agreed that to keep up with AI's explosive growth, standardization has to move upstream. Standards used to be set after a technology matured; now key parameters (such as modulation and the FEC framework) are locked in first so the ecosystem (IP, modules, cables) can develop in parallel.

Divergence: The Role of Copper in the 400G Era

Cisco still sees copper holding its advantage inside the rack, but Meta and other experts noted that as speeds double, copper reach keeps shrinking, which will push the industry toward optics or active cables (ACC/AEC) earlier in the 400G generation. The choice between PAM4 and PAM6 is also still debated: the center of gravity remains PAM4, but PAM6 stays on the table to help hit power targets.

Supply Chain and Market Impact: The Simple Tech Trend View

Judging from the OFC 2026 discussion, 400G per lane is not just a doubling of speed. It is a head-on contest between the Ethernet ecosystem and proprietary architectures such as NVIDIA InfiniBand.

The inflection point for silicon photonics and CPO: As loss on 400G electrical paths grows, CPO and NPO will no longer be lab technologies but the inevitable path to solving 1.6T/3.2T power. This has major financial implications for TSMC's COUPE packaging technology and for the silicon photonics plans of module and chip vendors such as Innolight and Marvell.
A windfall for IP vendors: IP leaders such as Synopsys will benefit from rising SerDes complexity. With physical-layer difficulty growing exponentially, the bar for in-house silicon rises and more companies will rely on proven 400G IP.
A strategic window for LPO/LRO: To cut power, retimer-free linear-drive solutions (LPO/LRO) will have more room to survive in the 400G generation. That raises the linearity bar for optical components and favors vendors with leading signal-processing technology.