Paper Analysis | Breaking the 400G-per-Lane Limit: Component and System Tradeoffs in IM/DD Interconnects | Coherent
With AI/ML applications growing explosively, cloud workloads are rising at an unprecedented pace. To keep up, intra-datacenter interconnects are trying to push per-lane rates from today's 200 Gb/s to 400 Gb/s. That would double switch throughput, raise integration density and lower cost per bit. The road is hard, though: electrical loss and chromatic dispersion stand in the way. This OFC 2026 paper from optical leader Coherent explores how component innovation and system-level optimization can meet that challenge within an IM/DD (intensity modulation / direct detection) architecture.
Reference
Title: Scaling IM/DD Interconnects to 400 Gb/s per Lane: Component and System-Level Tradeoffs
Authors: Anna Tatarczak, Roberto Rodes, Andrei Kaikkonen, Young Kai Chen, Julie Eng
Affiliation: Coherent Corp.
Venue: OFC 2026
Figure-by-Figure Analysis
The core message of the paper is that component bandwidth must exceed the 100 GHz threshold to support 400 Gb/s per lane with PAM4.
Figure 1: Frequency response of key 400G components and simulated eye diagrams
This figure shows measured performance on both the transmit and receive sides:
a) InP Diff-EML response: measurements show the 1310 nm indium phosphide (InP) differential electro-absorption modulated laser (Diff-EML) exceeds 100 GHz of bandwidth. At 20 degC it requires a drive swing of 2.0 Vppd.
b) 400G IM/DD driver: the electrical driver, co-designed with the modulator, also shows more than 100 GHz of bandwidth.
c) Simulated transmitter eye: with optimized PCB routing and a 20-tap FFE equalizer, the extinction ratio (ER) at 426 Gb/s is 4.9 dB and TDECQ (transmitter dispersion eye closure quaternary) is only 1.5 dB. Linearity stays good even at this extreme speed.
d) Receiver PD and TIA: an InP back-illuminated photodiode (PD) flip-chip bonded onto a transimpedance amplifier (TIA) also achieves more than 100 GHz of bandwidth.
Figure 2: 200G vs. 400G PAM4 link budget analysis
Doubling the rate comes with clear physical sacrifices:
Sensitivity penalty: simulations show that going from 212.5 Gb/s to 425 Gb/s costs about 5 dB of receiver sensitivity.
Noise vs. responsivity tradeoff: to reach >100 GHz bandwidth, the 400G receiver's TIA input-referred noise (IRN) rises from 18 pA/Hz^2 at 200G to 30 pA/Hz^2, and PD responsivity drops from 0.7 A/W to 0.5 A/W.
Performance limits: the figure shows that at low received optical power (Rx OMA), performance is limited by receiver noise; at high power, transmitter nonlinearity and laser relative intensity noise (RIN) dominate.
Conclusion: What This Means for the Industry
The paper shows that 400 Gb/s per lane IM/DD is technically feasible, but it is a hard-fought balancing act among bandwidth, noise and power.
A win for materials science: indium phosphide (InP) currently performs strongly in the race beyond 100 GHz, while silicon photonics (SiPh), despite its scale advantages, still struggles to reach the 70-80 GHz-plus bandwidth 400G requires.
A boost for AI compute: with more than 90% of intra-datacenter links shorter than 30 meters, 400G per lane can significantly raise interconnect density in compute clusters.
Volume-production challenges: the lab data look good, but commercialization still requires solving high-frequency packaging parasitics (e.g., flip-chip vs. wire-bond), thermal management, and the power pressure from more capable DSPs.
The keyword for the 400G era is no longer just "faster lasers", but "tighter system-level co-optimization".
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