OCP Global Summit 2026 | Astera Labs | Chris Blackburn, Jignesh Shah | Light on the Horizon: Scale-Up Fabrics with NPO & CPO

1. Why Listen to Astera Talk About Optics

Astera Labs is the archetypal vendor on the "electrical side" of the AI rack: Aries retimers, Taurus AEC modules and Scorpio fabric switches all exist largely because copper cannot reach far enough. A company like that taking the stage at OCP's photonics track (OCP Special Focus: Photonics) is a signal in itself.

Chris Blackburn (Director of Platform Solutions Architecture) covered systems and copper; Jignesh Shah (Sr. Director of Product Marketing, Signal Connectivity Group) covered NPO and CPO. The talk did not contain a single pJ/bit or cost figure. Its value lies elsewhere: a company that makes its living on copper drew copper's exit path itself, and labeled every segment with a scale.

Astera's optical push did not start with this talk. In October 2025 it announced the acquisition of Germany's aiXscale Photonics, which makes precision glass couplers that couple fiber to photonic integrated circuits (PICs); Astera's press release said the deal is meant to develop photonic scale-up solutions. Shah also noted that the detachable fiber-to-package interface CPO needs was on display at Astera's booth.

2. Breaking Down Three Forces: Bigger Pods, Flatter Topologies, Faster Lanes

Astera summarized the changes in scale-up in a three-row table:

Trend	Today	Next generation
Scale-up pod size	8–72 XPUs per pod	144–1,000+ XPUs per pod
Topology	Scale-up in rack, scale-out beyond	Scale-up domain extends across a row of racks
Bandwidth	PCIe 5/6, 200G/lane	PCIe 7→8, 400G+/lane

The three rows say the same thing: scale-up must leave the rack, while the usable reach of every electrical lane is shrinking at the same time. Per the slide, as PCIe, UALink and ESUN move from 200G/lane to 400G/lane, bandwidth doubles, frequencies rise and electrical channel distance shrinks. Single-hop topologies cut latency and raise XPU utilization, but every XPU must then connect directly to a more distant switch.

Blackburn then listed five pillars of customer decision-making: performance, power, cost, speed to deployment, and reliability and serviceability, concluding that "no single technology wins on all five dimensions." That is the foundation of Astera's case for a hybrid approach.

3. Breaking Down 144 and 576: Where Copper's Boundary Sits

Astera splits clusters by workload. Training clusters run long, sustained all-reduce, need high bisection bandwidth and span long node distances, so optics enters scale-up there first. Inference clusters carry short-burst, latency-sensitive traffic, prioritize bandwidth per dollar and span short distances, so they stay mostly copper. The slide adds "but growing!" to the inference column, effectively admitting inference is only later, not exempt.

The scale thresholds read as three ranges, plus a 144-accelerator trigger line for optics:

• Up to 72: one rack, with a copper cable backplane as today's standard. NVLink, PCIe and UALink remain viable over copper this generation and next. DACs, ACCs and AECs handle rack-to-rack links.

• Beyond 144: the slide says "pod sizes beyond 144 GPUs require physical distances that need the reach of optics." By STT's math, 144 is two 72-accelerator racks.

• 72 to 576: a hybrid pod with a copper backplane in the rack and NPO between racks, either direct to GPU or switch to switch. The speakers said today and the next generation fall in this range.

• Beyond 576: a fully optical pod with dedicated compute and switch racks, tied together by NPO/CPO; the slide gives no timeline, while Blackburn said "2 to 4 years" orally.

▲ Astera's scale-up boundaries: in-rack copper up to 72 XPUs, in-rack copper plus rack-to-rack NPO from 72 to 576, and all-optical NPO/CPO beyond 576 (Image source: Simple Tech Trend original; data from Astera Labs, 2026 OCP Global Summit presentation)

576 matters because it confines NPO's first market to "rack-to-rack links within eight racks", not the in-rack backplane. Compare OCP APAC Summit 2026 | SemiAnalysis | Scale Up Sophistry: neither side expects in-rack copper to be replaced in these two generations; the difference is that Astera explicitly hands the rack-to-rack segment to NPO.

▲ A hybrid pod uses a copper backplane for in-rack scale-up and NPO for rack-to-rack links, targeting 72 to 576 XPUs; an all-optical pod targets more than 576 (Image source: Astera Labs | 2026 OCP Global Summit presentation)

4. Breaking Down the Seven-Step Ladder: Where Signal Conditioning Disappears

Shah used a seven-step ladder to show the evolution: passive DAC up to 3 m, ACC up to 4 m, AEC up to 7 m, then AOC, LPO, NPO and CPO all beyond 50 m. The power and latency labels are telling: AOC is "high power, high latency," LPO and NPO return to "low power, ultra-low latency," and CPO is "lowest power, ultra-low latency."

▲ The seven-step interconnect ladder from passive DAC to CPO, with copper reaching 3 to 7 m and optics beyond 50 m; on the right, how copper cable gauge thickens as data rates rise (Image source: Astera Labs | 2026 OCP Global Summit presentation)

Shah's principle is to architect "as far to the left as possible," using copper wherever it works. Read from another angle, though, the chart is a map of where signal-conditioning silicon lives: AECs rely on retimers, AOCs and conventional optical modules rely on DSPs, LPO and NPO move to linear optics, and CPO, on Astera's own slide, needs "no additional signal conditioning in end-to-end link."

▲ Reach, power and latency of the seven interconnect steps, and whether each step keeps an electrical pluggable interface and signal-conditioning components (Image source: Simple Tech Trend original; data from Astera Labs, 2026 OCP Global Summit presentation)

Another argument is cable thickness: the higher the data rate, the thicker copper must be to cover the same distance, which becomes a physical bottleneck inside the chassis and backplane, while fiber thickness does not change with data rate.

5. NPO vs. CPO: Why Astera Is Betting on NPO Near Term

In Astera's NPO-versus-CPO table, the rows worth reading are the first, the last and the form-factor row in the middle:

Item	NPO	CPO
Beachfront density	Enough for near-term applications	Scalable for future high-radix applications
Power	Significantly lower than pluggables	Lowest of all optical architectures
Serviceability	Good, electrically detachable like pluggables	Difficult (if the optical engine is integrated with the switch/XPU)
Form factor commonality	Copper and optics	Optics only
Manufacturing complexity	Low, leverages existing ecosystem	High, new ecosystem of partners needed
Most likely use case	Near-term multi-rack AI scale-up	Next-generation switch and XPU platforms

▲ Astera's six-item comparison of NPO and CPO: the NPO form factor can be shared by copper and optics, while CPO is optics-only (Image source: Astera Labs | 2026 OCP Global Summit presentation)

The case for NPO has two layers. Manufacturing: optical engines can be built and tested by existing pluggable module makers, so assembly yield stays with them and the system side only integrates; CPO instead requires OSATs and advanced packaging houses to take on optical packaging. Timing: Shah believes NPO's beachfront density is enough for "the next few years," while CPO's high-radix advantage is needed only "two or three years plus" out.

This points the same way as ECOC 2026 | Huawei Scores CPO vs. NPO, and NPO Leads 4:2, but Astera adds a dimension Huawei did not stress: the same near-package socket takes copper today and optics tomorrow. The near-package board on the slide, with copper cable connectors on one side and optical engines on the other, is that claim in picture form. Shah also said recent NPO standards accept copper in the same form factor, a sign that "socket commonality" is moving into standards; for another strand of NPO standardization, see ECOC 2026 | Ciena Turns the 6.4T Optical Engine Back Into Shelf Stock With Open CPX.

6. Risks and Counterarguments

• A position without numbers: the slides name metrics such as pJ/bit and W/Tbps, but the talk gave no pJ/bit, wattage or cost values; NPO "significantly lower than pluggables" and CPO "lowest" are qualitative.

• Position aligned with business interest: hybrid architecture, electrical detachability and a socket shared by copper and optics each preserve a place for retimers, AECs and switches. This is the best case for an electrical-side company.

• 576 is a target, not shipments: the slide says "targeted towards." The inter-rack fiber cabling an eight-rack hybrid pod needs, and the on-board fiber routing NPO requires (which Astera itself lists), have no volume deployments yet.

• Inference clusters may move to optics sooner than expected: Blackburn cited the view that inference became the majority of AI workloads this year, but if inference also moves to large pods (agentic inference on the slide is one example), the "inference uses copper" premise could loosen earlier than 2 to 4 years.

• 400G/lane is the real test: the claim that "this generation and next can still use copper" depends on whether in-rack copper backplanes keep usable reach and cable thickness at 400G/lane.

7. What It Means for Taiwan's Supply Chain

• In-rack copper backplanes and rack-to-rack AECs have at least two more generations. Astera says NVLink, PCIe and UALink can stay on copper this generation and next, with DACs, ACCs and AECs still handling short rack-to-rack links. For Taiwan's cable assemblers and backplane connector makers, that signals continued demand, not a countdown to exit.

• NPO manufacturing stays with module makers, a window for Taiwanese optical module and assembly houses. Astera stresses that NPO reuses the front-panel pluggable manufacturing and test ecosystem; CPO, by contrast, requires OSATs and advanced packaging houses to take on optical packaging, a different bar from current module makers' capabilities.

• A socket shared by copper and optics is a double opportunity for connector makers. The same near-package position must accept both copper cables and optical engines; connector makers that can supply both versions will not be displaced when customers switch.

• Astera's chips are made by TSMC: Astera's FY2025 annual report (10-K) states that all of its ICs are fabricated by TSMC; the talk named no Taiwanese partners, and other supply relationships are outside the scope of this article.

8. Conclusion

The value of this talk is not in technical detail but in an electrical-side company writing the boundary down as numbers: in-rack copper up to 72 accelerators, in-rack copper plus rack-to-rack NPO from 72 to 576, fully optical only beyond 576, on a 2-to-4-year timeline given orally by the speakers. Its three reasons for choosing NPO (electrical detachability, a socket shared by copper and optics, manufacturing that stays in the existing ecosystem) protect both customer flexibility and Astera's own position.

STT's view is that Astera is betting the boundary moves slowly. If the first cross-rack scale-up pods ship as copper backplanes plus NPO in 2027 to 2028, Astera's retimers, AECs and switches all find a place in the hybrid pod; if switches jump straight to CPO, or in-rack copper gives way early at 400G/lane, the line on its own slide, "no additional signal conditioning," becomes its biggest risk. The thing to watch next is when aiXscale's coupling technology becomes an Astera optical product.

Copper built the foundation and optics will build the ceiling; what Astera wants to sell is the socket layer in between.

This article is for technology and industry trend analysis only and does not constitute investment advice.