OFC 2026 - A Paradigm Shift in Silicon Photonics Simulation: GF and Cadence Push Photonic-Native Compact Models - GlobalFoundries / Cadence

Introduction: The Optical Design Bottleneck in the AI Compute Race

As AI and high-performance computing (HPC) push data bandwidth demand into exponential growth, optical communications is shifting from traditional pluggable modules toward co-packaged optics (CPO) and large-scale integrated silicon photonics (SiPh). Yet conventional electronic design automation (EDA) tools face serious challenges in handling the physics of light.

At OFC 2026, GlobalFoundries (GF) and Cadence jointly presented their latest "Photonic-Native Compact Modeling" technology. The core of the work is breaking away from the traditional electronics-centric simulation framework and embedding optical physics directly into the EDA workflow, solving the accuracy and efficiency pain points that arise when silicon photonic systems scale to large integration levels.

Core Technology: From Electronics-Centric to Photonic-Native

1. Limits of Conventional Modeling: Poor Efficiency and Distorted Accuracy

The conventional approach forces optical signals into equivalent electrical quantities (V, I), which creates heavy computational overhead for bidirectional, multi-mode and multi-channel systems.

• Convergence errors and instability: forced electrical conversion causes numerical instability and limits scalability.

  
  

• No handling of reflections and crosstalk: traditional tools assume signals flow in one direction and cannot accurately capture back reflections or inter-channel crosstalk in optical circuits.

  
  

2. The GF Fotonix™ Platform and the Native Modeling Framework

GF's solution is built on its 300mm monolithic silicon photonics platform (GF Fotonix™), which integrates 45nm-class RFCMOS technology with standard digital logic cells.

The new Photonic-Native framework builds waveguide scattering principles directly into Verilog-A models:

• Multi-dimensional data on a single port (Optical Port Methodology): a single schematic connection captures both incident and outgoing waves, enabling true bidirectional simulation.

  
  

• Major simulation speedup: data show that for large circuits with more than 10,000 components, native modeling delivers a 2x simulation speedup compared with the conventional conversion approach.

  
  

• Simpler models: thanks to a leaner structure, the number of model files drops by 40%.

  
  

Key Data and Hardware Correlation

The credibility of any modeling technology rests on hardware validation. GF says its photonic component library already includes more than 80 hardware-validated SiPh components.

1. Simulation Accuracy for Key Components

• Microring modulator (MRM): the model accurately predicts photocurrent trends across bias voltages and optical power levels, which is critical for the thermal feedback loop in driver design.

  
  

• Bandwidth prediction: at -1V DC bias and 2Vpp, the model accurately matches the trade-off between ER (extinction ratio), IL (insertion loss) and bandwidth.

  
  

2. System-Level Validation Cases

Validation case	Technical focus	Measured result
Sagnac-based circuit	Validates bidirectionality	Successfully captures the interference physics of clockwise and counter-clockwise waves in a single waveguide.
Multi-wavelength WDM system	Validates multi-channel scalability	Simulates all channels simultaneously and accurately captures thermal coupling and crosstalk between microring modulators.
Large cascade of bends	Validates reflection-induced effects (ORL)	Successfully reproduces the reflection peaks produced at a 25μm bend radius.

Supply Chain and Market Impact: The Strategic Role of EDA

The GF–Cadence collaboration marks a key shift in the silicon photonics supply chain:

1. Foundry (GF): by offering a highly integrated, hardware-validated PDK, GF is positioning its Fotonix platform as the foundry of choice for 1.6T-and-beyond optical products, especially in CPO and AI active cable modules.

2. EDA (Cadence): by integrating the Spectre Photonics engine, Cadence is cementing its lead in electro-photonic co-design and reducing the friction customers face when switching between tools.

3. End users (AI/HPC vendors): faster virtual prototyping shortens design cycles (TTM), resolving issues such as optical return loss (ORL) and modulation crosstalk before tape-out.

   
   

Simple Tech Trend View: The Era of Automated SiPh Design Has Arrived

"Photonic-native modeling" is not just about speed; it is a necessary step toward automated silicon photonics design.

• Outlook: we expect this photonic-native simulation approach to become the industry standard within the next 12–24 months. As silicon photonic chips scale from dozens of components to thousands or even tens of thousands, any non-native conversion approach will break down under the computational load.

• Key watch item: GF's roadmap mentions support for "customized doping recipes", meaning the PDK will give designers more freedom to optimize PN junction performance for specific applications. This will be at the heart of the next wave of silicon photonics performance gains.

  
  

Silicon photonics is no longer just about the quality of optical components; it is about the maturity of the design environment. The flow GF and Cadence showed at OFC 2026 closes the last gap between silicon photonics physics and large-scale electronic design automation.