AMD's Streshinsky on Silicon Photonics: Scale-Up Bandwidth in AI Racks Can Only Be Handed to Light

1. The real thread of this talk isn't "how great silicon photonics is" but an underrated number: scale-up bandwidth inside the rack is nearly an order of magnitude larger than scale-out bandwidth to the outside world. As racks keep growing, electrical signaling hits the physical ceiling of bandwidth × distance, and optical interconnect goes from "an option" to "the only answer."

2. The optical chiplet AMD showed uses micro-ring resonators to stack 16 wavelengths on a single waveguide, all running power-saving NRZ on-off keying. The chip is under 10 mm², runs 50 Gbps per lane, and reaches a 10⁻¹² class error rate without FEC. Micro-rings beat MZMs on three counts taken together: area, native multi-wavelength support, and energy efficiency.

3. Heat remains silicon photonics' Achilles' heel — silicon's thermo-optic coefficient makes every ring resonator drift, so each ring needs its own micro-heater and control circuit. The most pragmatic line of the talk: only when you add up the light source, laser, driver, TIA, heaters and cooling do you have "energy efficiency"; comparing chip-only pJ/bit is not a fair comparison.

1. Why This Talk Is Worth Your Time

The speaker is Dr. Matthew Streshinsky, Senior Director of Photonics at AMD. His background is practically a summary of this wave of silicon photonics commercialization: co-founder and CEO of silicon photonics startup Enosemi, which was acquired by AMD; before that, a founding team member at Elenion Technologies, and after Nokia acquired Elenion he took over Nokia's silicon photonics engineering. A serial founder who has seen bubbles and actually sold companies. When someone like that talks silicon photonics, the point isn't the specs on the slides but "what's real and what's still vaporware."

This was an invited technical talk hosted by the IEEE Photonics Society Taipei Chapter at National Taiwan University (NTU), titled "Silicon Photonics for Future AI Interconnects." Below are the key points and the live Q&A, with the published chiplet from the second half broken down in detail.

2. The Starting Point: Why AI Suddenly Devours Bandwidth

The first part of the talk explained why compute demand is exploding, since that is the root of all optical interconnect demand.

The real inflection of the past year is that AI went from "a fun toy" to "a tool that actually boosts productivity" — code gen, Codex, ChatGPT and the like now deliver real value. That brings two qualitative changes. First, we're no longer "sending a query, running the model once, getting tokens"; instead, agents compute continuously in the background, performing relatively complex tasks back to back. Second, reasoning and verification workloads mean doing one thing takes far more compute than before; add multimodal, and the input isn't just text but video, 3D and all kinds of sensor data.

Streshinsky added an often-overlooked driver: distillation. Once models are distilled down, they fit on phones, laptops and edge devices, so they get deployed more widely — and the wider the deployment, the more total inference compounds exponentially. Training keeps pushing per-model compute higher, while inference expands with endless use cases; together they drive compute demand ever upward.

On the hardware side, this maps to AMD's recently announced rack-scale system (Helios, as mentioned in the talk): a full rack of GPU trays plus switches. Compute scale only keeps growing, and as it does, "how to connect all these chips to each other" becomes the bottleneck.

3. The Real Wall Is Scale-Up, Not Scale-Out

This is the most important slide of the talk — and the one outsiders most often get confused about.

Streshinsky splits the network into two layers. Scale-out is the Ethernet layer that connects the rack to the outside world and feeds data in and out; scale-up is the layer that connects every compute device "inside" the rack to each other. The key number: scale-up bandwidth is nearly an order of magnitude larger than scale-out.

Keep that order of magnitude in mind, because it's the fundamental reason silicon photonics is so hot right now. As we go from one rack to multiple racks, scale-up instantly exceeds what pure electrical cabling can connect — electrical signals can't keep up, so you have to switch to fiber. This is optical demand that "appears out of nowhere, nearly an order of magnitude larger." Scale-up used to be copper's domain; now it is being forced to go optical.

4. Copper's Physical Ceiling: Bandwidth × Distance

Why can't copper hold up? The answer isn't "copper is bad" but a very hard physical quantity: the bandwidth-distance product.

Historically, the boundary between electrical and optical signaling has sat around 100 Gbps·m — meaning you can have high bandwidth or long distance, but once their product crosses that line, copper loses across the board on cost, power, reach, and even size and weight. Telecom networks spanning hundreds of kilometers could never use copper; now, cloud data centers — rack to rack, and even inside the rack — run bandwidth so high that the line is crossed within just a few meters.

Even worse are retimers. When electrical signals can't travel far enough, you have to insert retiming devices to regenerate them, and every retimer stage adds cost, complexity and power — at scale, these regenerators alone eat a meaningful amount of power. That's the key reason all-electrical solutions can't go further.

5. From Pluggables to CPO: Moving Optics Step by Step Toward the ASIC

Streshinsky drew the evolution of optical interconnect as an "integration ladder"; each rung moves the electrical-to-optical conversion a bit closer to the ASIC:

• Pluggables: The compute chip sends electrical signals across the board to a front-panel slot, where they are retimed or amplified and converted to light. Lowest integration, and today's mainstream.

• Onboard optics: The optical engine moves from the front panel onto the board, next to the package, shortening the electrical channel and saving some energy. The cost is serviceability — you can no longer just pull a failed unit like a pluggable, so additional reliability proof is required.

• Co-Packaged Optics (CPO): The electrical-to-optical conversion sits right next to the ASIC, on the same substrate. This is where silicon photonics really shines — using silicon as the material system to integrate optical conversion right up against the ASIC.

• The future: No retimers at all; the ASIC drives the optical devices directly. He himself said "it's debatable whether this is the right approach," and others at the event are pursuing alternatives such as microLED.

We explain in more detail why CPO is an advanced packaging war in "The Paradigm Shift in Photonic Packaging: Why CPO Is an Advanced Packaging War" (in Chinese); this talk adds the physical reasons why climbing to the CPO rung is unavoidable.

6. Why Silicon Photonics Is a Must: Give the Saved Energy Back to the GPU

The core incentive for climbing this ladder comes down to one word: energy.

The energy needed to transmit an electrical signal rises with distance. So the closer you push chips together — and the closer you push the electrical-to-optical conversion point — the more power you save. Streshinsky gave a very concrete comparison: for a roughly 200 Gbps lane, copper needs about 4-5 mW/Gbps and must handle about 30 dB of channel loss to push a meter or two, roughly 200 mW; with the optical engine right next to the package traveling just a few millimeters, it can drop to under 100 mW.

Multiply that gap by the system's roughly 230 PB/s of total bandwidth and the power savings are enormous — and every watt saved can be handed back to the GPU to make it stronger, while cooling gets easier too. It's a whole chain of system-level benefits.

Another often-overlooked but equally critical dimension is area. The silicon area needed for these ultra-short-reach interconnects is far smaller than for long-haul link components; smaller area means more bandwidth per unit area and per unit of shoreline (chip edge length) — and bandwidth density per area/shoreline is one of the most important metrics for building these systems.

7. Breaking Down AMD's 16-Wavelength Optical Chiplet

The second half of the talk moved to the published implementation. This is the essence of understanding how silicon photonics actually packs so much bandwidth into a single fiber, so let's break it down.

First, the standard and the packaging form factor. To make optical components from different vendors interoperable, AMD, Broadcom, Nvidia and several adopting customers are pushing scale-up into a standard (multi-source agreement in nature) — not just "interoperable," but agreeing on which wavelengths and what speeds. The first spec deliberately uses the simplest signaling: on-off keying of light (NRZ / OOK), because for basic optical communication it's the most power-efficient both optically and electrically. The first spec is 4 wavelengths per direction, bidirectional over a single fiber, at 50 Gbps per wavelength.

Why bidirectional? The key is radix. A switch's total bandwidth is finite, say 100 Tbps; if all 100 Tbps were packed into one unidirectional fiber, that fiber could reach only one destination. Sending light both ways in the same fiber uses the fiber plane more efficiently and supports the large switch radix that scale-up requires.

What the optical chiplet looks like. Inside that gray box is a silicon photonics chip integrating filtering, detection and modulation, attached to a bundle of group fibers, with various circuits integrated in the package to boost density. The core is multi-wavelength communication; let's follow the signal flow:

• Input: Up to 16 wavelengths are coupled in, spaced about 200 GHz apart (about 0.75 nm), and first split into even and odd channels.

• Modulation (transmit): Using micro-ring modulators — resonant cavities that selectively modulate the intensity of just one specific wavelength. Placing 8 micro-rings on one bus waveguide lets 8 wavelengths go on the upper path and 8 on the lower path, 16 modulators in total (8 per path). Each path modulates wavelengths at 400 GHz spacing, which are then recombined into a single waveguide and coupled into one fiber.

• Demultiplexing (receive): The 16 modulated wavelengths come in and are again split into even and odd paths, so adjacent channels are spaced further apart — this is to reduce crosstalk. Demux uses second-order filters: two coupled ring resonators forming a sharper narrowband drop filter than a first-order one. The cost is more complex tuning; the benefit is cleanly "picking" each wavelength and sending it to a photodetector to convert back to electrical. Eight on one waveguide, eight on the other, back to 16.

• Integration density: Six such circuits (he calls each a bank) sit on one chip, giving 6 × 16 of receive bandwidth. In the die shot, the silicon photonics chip faces up with the electrical IC stacked face-down on top; the whole thing is under 10 mm², at 50 Gbps per channel.

Measurement results: They built error-rate self-test into the chip and measured 50 Gbps NRZ per channel with all 16 channels running, showing receive-side eye diagrams with quite good end-to-end BER — and without FEC (forward error correction). This shows the approach works and complexity is manageable.

8. Why Micro-Rings Instead of MZMs

Someone in the audience asked this, and it's key to understanding the chip's design philosophy. Compared with the Mach-Zehnder modulator (MZM, usually a traveling-wave device) common in optical communications, micro-rings were chosen for three reasons:

1. Area. A micro-ring has a radius of about 5-10 microns; an MZM with similar bandwidth, modulation depth and voltage swing would be on the order of millimeters — thousands of microns long. High bandwidth density demands small enough devices.

2. Native multi-wavelength. Multiple resonators can couple to the same bus waveguide, which is itself the most natural way to implement WDM. With MZMs, you need extra mux/demux/remux circuitry — doable, but more cumbersome.

3. Energy efficiency. A micro-ring can be driven as a capacitive element with capacitance in the tens of fF (femtofarads); a traveling-wave MZM, by contrast, is a transmission line with tens of ohms of impedance, or pF-class (picofarad) capacitance when treated as a lumped element. That's a huge efficiency gap.

Of course rings have their cost: the control system is hard to build and micro-heaters take a lot of work. But once you tally energy efficiency and circuitry, rings come out ahead.

As for pushing bandwidth further, there are other paths and materials: thin-film lithium niobate (TFLN), SiGe quantum-well electro-absorption modulators tightly integrated with silicon, heterogeneously integrated InP devices, organic hybrid materials in slot waveguides, and even plasmonic devices built against metal. Each has its own challenges — exactly the problems he wants to hand to the research community.

9. Heat: Silicon Photonics' Achilles' Heel, and How to Lock the Wavelength

Any resonant device in silicon runs into the same problem: silicon has a thermo-optic coefficient. When temperature changes, the refractive index changes and the resonator's behavior drifts. This is one of silicon photonics' hardest challenges.

The fix: put a small resistive micro-heater next to every ring resonator, with control circuitry to compensate for temperature changes. Streshinsky showed a measured temperature ramp — temperature deliberately varied over time, the heaters tracked it in real time, and net BER stayed unchanged, meaning the signal stayed locked on the right wavelength. Being able to control this across a wide operating temperature range, and even under relatively fast temperature swings, is one of the keys to whether such systems can go live.

And don't forget there's a very hot GPU sitting right next to it. The GPU's thermal effect on this silicon is a variable the whole package and thermal design must account for — a multi-scale problem that runs from device-level physics all the way to the system level.

10. The Scorecard, How to Scale Further, and a Few Questions Without Standard Answers

The link's scorecard (key metrics from Streshinsky): BER reaches 10⁻¹² with a small amount of retry allowed, which is enough for scale-up networks; on reach, these scale-up pods are large but won't need more than 100 meters in the next few years; bandwidth per fiber = 16 wavelengths × 50 Gbps; latency is low because NRZ on-off keying needs no FEC and retiming is fast; on efficiency he minimized laser power and showed single-device energy well below the roughly 5 pJ/bit manufacturable reference line he mentioned earlier; shoreline density reaches the terabit/s-per-millimeter class.

How to scale further. To keep doubling per-fiber bandwidth the way network bandwidth does, there are two clear paths: raise the per-wavelength modulation rate from 50 Gbps to 100 Gbps, or increase wavelengths from 4 to 8 to 16. But neither can "spend 2x the power for 2x the bandwidth" — chips are already as close as they can get, so going further requires fundamental efficiency innovation. And going from 4 to 16 wavelengths at the same spacing means handling 4x the optical bandwidth, which makes device design much harder; raising the rate also can't just mean lowering the ring's Q (which widens optical bandwidth but hurts efficiency and requires more power). Further out are dual polarization (very hard) and higher-order multilevel modulation (PAM). He explicitly framed these as a "call to action" for the researchers in the room.

A few exchanges from the live Q&A that have no standard answer but are full of substance:

• External or integrated light source? Start with an external light source, because the failure Pareto usually lands around the source — not necessarily a dead diode, but often dust contamination in the optical path, or failing DC-DC converters or TECs. External = pluggable and replaceable = serviceable. Once reliability and cost are proven, there's room to move to onboard heterogeneously integrated lasers; he noted Intel has already published good reliability data on heterogeneously integrated light sources. As for a single DFB versus a laser array? Both are possible, depending on whether a multi-wavelength matched array can be made with good yield and a cost advantage. This pairs well with NVIDIA's push to rewrite optical interconnect economics with DWDM laser arrays.

• Heat and warpage — will glass substrates become a trend? Warpage is definitely a real problem — chips, interposers and substrates keep getting bigger, while fiber alignment needs micron-level precision; when silicon warps, the beam walks off. Glass substrates have lower CTE, good optical properties, and can thermally isolate adjacent chips, making them a toolbox option worth watching, but he wouldn't call it an industry trend.

• Will modulation voltage go up? The hope is to keep it as low as possible, ideally CMOS-compatible; sub-3V is hard but achievable.

• MicroLED, coherent, or silicon photonics — which is most power-efficient? His answer was candid: a fair comparison has to be end-to-end ASIC-to-ASIC energy (including laser, amplifiers, drivers, TIA and gearbox); comparing chips alone isn't fair. And the use cases aren't apples-to-apples — microLED suits many-fiber compute-to-memory links up to about 10 meters, while silicon photonics targets tens of meters up to 100 meters. There's no public one-to-one comparison at the same bandwidth density and application yet, so there's no standard answer to who's most efficient; what really decides the choice are system-level trade-offs in packaging, thermo-mechanics and gearboxes.

11. Conclusion

The most valuable takeaway from this talk isn't any single spec but a clear causal chain: AI pushes scale-up bandwidth an order of magnitude above scale-out → electrical signaling hits the bandwidth × distance wall → optical interconnect goes from option to the only answer → silicon photonics, winning on both efficiency and area, becomes the most likely vehicle. AMD's 16-wavelength micro-ring chiplet is concrete proof of that chain landing as something "manufacturable, interoperable and thermally controllable."

But Streshinsky didn't oversell it either. Every further doubling of bandwidth can't cost twice the power; heat, light-source reliability, package warpage and fiber alignment are all still tough nuts to crack. The line he kept repeating is really meant for the whole industry: energy efficiency can't be judged at the chip alone but across the full ASIC-to-ASIC link; and a standard can't belong to one company — optical engines from different vendors must speak the same language. Silicon photonics is winning on clear direction today, but whether it keeps winning depends on whether these system-level engineering details get solved one by one.

One thing for readers to track: what's worth watching next isn't "whose single lane got faster," but who first raises wavelength count or modulation rate without sacrificing energy efficiency — that's the real watershed in this race.