Paper Analysis | Integrated Glass Waveguide Substrate with Surface-Coupled Photonic Chips for Massive CPO Scaling

Introduction

With the explosive growth of artificial intelligence (AI), data center demand for high bandwidth and low power has reached a tipping point. To shorten electrical signal paths and reduce loss, moving optics inside the electronic package — co-packaged optics (CPO) — has become an inevitable trend. Yet precisely and quickly integrating silicon photonic integrated circuits (PICs) onto high-density circuit substrates while keeping coupling loss low has long been a major pain point for volume production. Corning's answer is a glass substrate with embedded ion-exchanged (IOX) waveguides that uses evanescent coupling to try to clear the last mile to CPO volume manufacturing.

Source for Readers

• Title: Integrated Glass Waveguide Substrate with Surface Coupled Photonic Chips for Massive Scaling of CPO

  
  

• Authors: Lars Brusberg, Seong-ho Seok, Tim Grygiel, et al.

  
  

• Affiliation: Corning Optical Communications (research centers in Germany, Korea and the US)

  
  

• Venue: OFC 2026 © Optica Publishing Group 2026

  
  

In-Depth Figure Analysis

Figure 1: Integrated Glass Waveguide Substrate Architecture

This figure shows both the macro vision and the micro structure of CPO:

• Fig 1a: a glass substrate with 16 PICs arranged around an ASIC. This layout keeps electrical trace length under 13 mm, maximizing transmission efficiency.

  
  

• Fig 1b & 1c: the heart of the paper — ion-exchanged (IOX) waveguides embedded inside the glass substrate, with flip-chip assembly via gold bumps in an etched cavity.

  
  

• Why it matters: it proves the optical interface (waveguides) and electrical interface (gold bumps) can sit on the same surface and be assembled simultaneously, with placement time under 5 minutes per PIC — critical for high-volume manufacturing.

  
  

Figure 2: Test Vehicle Design and Coupling Efficiency Simulation

• Fig 2a: a surface coupler designed with eigenmode expansion (EME) simulation, transferring light between the IOX waveguide and a SiN waveguide.

  
  

• Fig 2b: the data show that with a SiN taper length of 2–3 mm, coupling loss drops below 1 dB while tolerating lateral offsets of up to 3–4 µm — well within the comfortable precision range of automated assembly tools.

  
  

• Fig 2c & 2d: the fabricated glass interposer, including a 16-waveguide array, alignment marks and electrical pads inside a 22 µm-deep cavity.

  
  

• Why it matters: this defines the process window and proves glass substrates can provide low-loss (<0.1 dB/cm), high-density interconnect real estate.

  
  

Figure 3: PIC Assembly Results and Performance Measurements

• Fig 3a–3c: viewed through the back of the glass substrate, the optical adhesive fills uniformly without overflow, and alignment accuracy is held within 1 µm.

  
  

• Fig 3e & 3f: measurements of the assembled electro-optical system show C-band coupling loss of about 3–4 dB, while pure optical assembly tests bring loss below 1.5 dB, with the best point even under 1 dB.

  
  

• Why it matters: it validates electrical integrity (a daisy-chain test across 96 gold bumps with resistance as expected) and the thermal stability of optical transmission.

  
  

Conclusion

Corning's results this time are impressive. The glass substrate is no longer just a "transparent support" but a "functional carrier" with high-density optical and electrical interconnect capability.

1. Volume-production potential: optical alignment used to demand extreme precision and time; by relaxing tolerance to 3–4 µm through evanescent coupling and completing single-PIC assembly in 5 minutes, Corning delivers a qualitative leap in throughput.

   
   

2. Higher bandwidth density: shrinking waveguide pitch to 50 µm would let a single module deliver up to 8 Tb/s of bandwidth density (400G per waveguide), squarely matching the appetite of next-generation AI clusters.

   
   

3. Simpler packaging: electrical and optical interfaces are completed in the same assembly step, reducing process complexity, and glass's coefficient of thermal expansion (CTE) is a closer match to the chips, a major advantage for long-term thermal stability.

   
   

In short, if this technology makes it into the supply chain, it will dramatically lower the barrier to CPO, turning "optics replacing electrical links" from a lab slogan into a cost-effective solution that can actually be deployed.

SEO description (meta description): STT analyzes Corning's OFC 2026 paper on using embedded glass waveguide substrates and evanescent coupling to solve CPO scaling, featuring <1.5 dB low-loss coupling, 8 Tb/s bandwidth density and 5-minute assembly.

Article excerpt: Glass substrates are making a comeback. Corning's latest paper shows a glass interposer with IOX waveguides and electrical interconnects that makes silicon photonics PIC assembly remarkably fast and achieves 8 Tb/s bandwidth density — an interconnect weapon for the AI era.

Suggested tags: OFC2026, CPO, Corning, Silicon Photonics, Glass-Waveguide, AI-Interconnect, Evanescent Coupling

Suggested URL slug: ofc2026-corning-glass-waveguide-cpo-scaling