ECOC 2026 | Five Standards Fight Over 0–10 km, One Covers 10–2,000 km: Nokia Lays Out the 1600G+ Option List — and Says "We Can't Build Them All"
Julia Larikova, VP of Product Line Management at Nokia, spoke on component challenges for 1600G+ at the ECOC 2026 Day 2 Market Focus. She didn't describe any single physical limit becoming the bottleneck. What she described was an explosion of options: power, baud rate, standards, form factors and applications are all diverging at once, and "build everything" simply isn't viable from an engineering standpoint.
The hardest-hitting chart: IMDD (FR-LR) reach falls from about 30 km at 400G to about 6 km at 800G, about 1 km at 1.6T, and zero at 3.2T; on the same chart, coherent lite holds steady around 20 km and CL+ stays at 80 km. The slide's third takeaway: at 1.6T PAM4, IMDD and coherent lite now have similar power requirements.
Another line sums up the absurdity: there are five standards between 0 and 10 km, and only one (ZR/ZR+) from 10 km to 2,000 km.
The power picture was also broken down: the optics barely moved, while the ASIC grew from about 8 W at 400G to about 24 W at 1600G, tripling — which is why every pluggable generation needs a new form factor.
On the 3.2T standards map, the METRO-to-LONG HAUL cells are simply printed Undefined.
Her product answer wasn't one but four: OSFP/XPO, OSFP-XD, ELSFP 2.0 and a full-band sled. Among them, XPO delivers 12.8 Tb/s per module and 204.8 Tb/s per 1RU switch — at the cost of going fully liquid-cooled.
1. Nothing Is Impossible to Build — There Are Just Too Many Versions to Build
Julia Larikova's first content slide was titled "Incredible range of challenges," subtitled "compared to previous generations." Five columns sit side by side: Power, Baudrates, Standards and interop requirements, Form factors and cooling approaches, and Applications.
The damage this table does isn't in any single column — it's in the Cartesian product once all five columns expand at the same time.
The power column lists ASIC power, drivers and TROSAs. The baud rate column covers lane rates from 100 Gb to 400 Gb, SiGe and CMOS challenges, and interconnect issues. The standards column lists DR/FR/LR IMDD, coherent lite (multiple FEC options and no standard yet), OIF ZR, and ZR+/ZR++. The form factor column runs from OSFP, OSFP-XD, XPO, FRO, LPO, NPO and CPO all the way to ELSFP 2.0. The applications column covers OCS, RF/S21 interoperability from CPO to NPO to LPO, ZR+ interoperability requirements beyond 1,000 km, full-band transponders, and SuperC / SuperL / S-band.
She was blunt on stage: for a company like Nokia that has to build all of these devices, this is an extremely difficult set of requirements from a development standpoint. You have to choose, because you can't build them all.
That line is the crux of the whole talk. It's actually the flip side of what Ciena said in the adjacent slot the same day: Ciena argued that standards are needed to focus engineering firepower, while Nokia said that until standards arrive, everyone is being forced to place bets.
2. The Truth About Power: The Optics Barely Changed — the DSP Did
The "Coherent DSP Power" slide opens with three takeaways:
DSP power for typical OIF ZR applications is growing faster than CMOS process nodes
Optics power won't be significantly affected until the 3.2T generation
Pluggables need a new form factor every generation
The bar chart on the right settles it: at 400 Gbps, the ASIC draws about 8 W and the optics about 7 W — roughly equal. At 800 Gbps, the ASIC jumps to about 16 W while the optics sit at about 7.7 W. At 1600 Gbps, the ASIC is about 24 W and the optics about 8.5 W. Over three generations the ASIC tripled while the optics essentially stood still.
The pie chart on the left explains why it's so hard to bring down: within DSP power, line accounts for 43% and analog for 43%, with client and control making up the rest. In other words, nearly 90% of the power sits in the line side and the analog front end — exactly the parts that benefit least from process scaling. You can move digital logic to a more advanced node, but the analog front end and line interface don't shrink proportionally.
The consequences show up directly in the mechanics: modules no longer fit in the original QSFP and must move to OSFP, then OSFP-XD. Every generation brings a new form factor, which means the supply chain has to retool molds and requalify thermals all over again.
This also answers a frequently asked question: why is the push toward CPO/NPO so strong? Because on the pluggable path, power is now growing faster than process technology can offset. We covered the upstream version of the same story in ECOC 2026 Light Sources Workshop: Lasers and Packaging Are the Real Bottleneck.
3. The Chart That Leaves IMDD No Room to Argue
If you only remember one chart from this talk, make it "IMDD & Coherent Lite Power."
Its three takeaways frame the problem first:
One standard covers every application from 10 km to 2,000 km — ZR/ZR+.
Between 0 and 10 km, there are five standards.
At 1.6T PAM4, IMDD and coherent lite now have similar power requirements.
The left chart shows power: IMDD is about 12 W at 400 Gbps, about 18 W at 800 Gbps, and about 25 W at 1600 Gbps, while coherent lite stays flat around 28 W and CL+ around 30 W. IMDD's power advantage has shrunk from a 16 W gap to just 3 W.
The right chart shows reach, and this one is the verdict: IMDD (FR-LR) still reaches about 30 km at 400 Gbps, about 6 km at 800 Gbps, about 1 km at 1600 Gbps, and zero at 3200 Gbps. At the same rates, coherent lite holds steady at 17 to 20 km and CL+ stays at 80 km throughout.
Read the two charts together and there's only one conclusion: at 1.6T, choosing IMDD no longer buys you lower power — only shorter reach. This isn't a "coherent is better" position statement; it's the fact of two curves crossing on a chart.
And the line "five standards for 0–10 km, one standard for 10–2,000 km" captures the industry's misallocation of resources more clearly than any complaint could: the most crowded standards fight is happening in the segment with the shortest reach and the smallest differences.
We broke down the related technical split in detail in ECOC 2026 Workshop: Fast-Narrow vs. Slow-Wide at 448G.
4. Baud Rate Is No Longer a Number — It's a Menu
The "Baud rates in different 1.6/2.4T applications" slide lays the DSP design problem out in three columns, each a different chip:
Low power: reach short, <40 km; baud rate 220–247 GBd; form factor / application OSFP, 1.6/3.2T coherent lite; power 30 W target; modulation 16QAM
Multi-haul: reach 40 km – 7,000 km; baud rate 100–260 GBd; form factor / application OSFP v5.21, 1.6T ZR/ZR+/ZR++; power 43 W; modulation 16QAM
High-performance: reach 40 km – 15,000 km; baud rate 60–300 GBd; form factor / application OSFP-XD v1.11, 2.4T high performance; power 60 W; modulation 64QAM
Look at the middle column: a single DSP has to support everything from 100 GBd to 260 GBd. That's exactly what Larikova stressed on stage — no one has ever designed a DSP with such a wide operating range, and the filter bank has to be chosen to work across the entire baud-rate span. The high-performance chip is even more extreme: 60 to 300 GBd, a 5x operating range.
The two boxes below fill in the standards status: 1600 coherent lite is being defined (<40 km, simplified client side, lower power); 1600 ZR and ZR+ have gone to straw ballot, covering OFEC, ZR 120 km single-carrier, ZR+ 1,000 km with two digital subcarriers, and MV-PCS for ZR+.
This is the closest thing to a "schedule" in the whole talk. 1600 ZR/ZR+ entering straw ballot means the standards path at the long-haul end is clear, while coherent lite at the short-reach end still has no standard — back to what the standards column on the first slide said: multiple FEC options, no standard yet.
5. Blanks on the Standards Map: The 3.2T Rows Read "Undefined"
The "Standards" slide is one big matrix. The horizontal axis is application and reach: INTRA-DC (500 m DR), CAMPUS (2 km / 4 dB IL, DR+/FR), ACCESS (10 km / 6 dB IL, LR), METRO (40 km ER), DCI (40–80 km "CL+"), LONG HAUL (80–120 km ZR) and SUBSEA (up to 1,000 km ZR+). The vertical axis is 400G, 800G, 1.6T and 3.2T, with each generation further broken out by lane configuration.
The 400G rows are fully populated: 400GBASE-DR4 / FR4 / LR4 / ER4, OIF 400ZR and OpenZR+ 400G. The 800G rows are still fairly complete: 800GBASE-DR8 / DR4 / FR4 / LR4, 800GBASE-LR1, 800GBASE-ER1, OIF 800ZR and 800G OR/ZR+ (PCS). TBDs start appearing at 1.6T, but the coherent row mostly connects: OIF-1600CL, OIF 1600ZR or CL, OIF 1600ZR, OIF 1600ZR+, and ZR++ or Proprietary.
Then comes 3.2T. After 2×1.6TBASE-FR4 comes Undefined. After 4×800GBASE-ER1 comes Undefined. After 2×OIF-1600CL, four consecutive cells read Undefined, and the last one reads Proprietary.
This table needs no interpretation. It is its own conclusion: the industry wants suppliers to start designing for 3.2T now, but more than half of 3.2T's destinations don't even have names yet. In Larikova's words, we're talking about designing a 1.6T DSP that is forward-compatible with 3.2T, while "the future is unknown and right now it's as blank as a sheet of paper."
What deserves even more attention is the last cell: Proprietary. When standards leave a blank, what fills it is each vendor's own solution — precisely the state the pluggable ecosystem has spent 25 years trying to avoid.
6. The Option Explosion Made Physical: Four Form Factors, Four Bets
If one DSP isn't enough, one form factor certainly isn't either. The "Application optimized form factors" slide lines up Nokia's four product lines:
OSFP / XPO: traditional coherent routing applications with a strict power envelope — CL, ZR, ZR+.
OSFP / OSFP-XD: also coherent routing, but with a relaxed power envelope to maximize performance.
ELSFP 2.0: integrates client-side (PAM4 IMDD) optics to simplify operations — especially with LPO/CPX switches.
Full-band Xponder: a full-band transponder with 12.8T on a single sled, supporting both pluggable and integrated client optics.
The most interesting part is a dedicated slide on the "Double-sided pluggable (media converter)." It shows the module's internals: XR6 1.6T Coherent TROSA + Huron 1600G DSP + ICE-D 2×DR4 or 2×FR4. Its job is to convert client-side IMDD PAM4 optical signals directly into line-side coherent optical signals — the front/client side being, for example, 2×800G-DR4 or 2×800G-FR4, and the back/coloured side PCS-16QAM, exiting through a blind-mate connector.
Then there's the scale: 16 modules plug into the same chassis, with mux/demux and booster/pre-amp built into the optical backplane, so a single line interface covers the entire band.
This is the implementation of what Larikova meant by "you can't just solve for CPO and LPO — you have to solve scale-out at the same time." A DSP that handles both client and line squeezes two previously separate worlds onto one board — saving not just power, but an entire layer of patching and operations in the data center.
She also spelled out the cost: the client-side interface isn't stable enough yet, and that part isn't standardized. Nokia alone has built roughly five different versions of this kind of platform.
7. XPO: 12.8 Tb/s per Module, 204.8 Tb/s per Switch — the Price Is Going Fully Liquid-Cooled
The spec ceiling of the talk is the "XPO — eXtra dense Pluggable Optics" slide.
12.8 Tb/s per module, built as 8 × 1600ZR/ZR+
Electrical side: 64 × 200G I/O; optical interfaces span DR, FR, LR, CL and ZR/ZR+
204.8 Tb/s per switch: 16 (8×2) XPO modules in 1RU, 21-inch rack width
Two XPO modules can fill the entire C-band or L-band, at 260 W to 320 W
Integrated liquid-cooling cold plate; inside the module is a three-layer card stack: the top and bottom cards each carry 32×200G I/O, while the middle card handles the blind-mate connector and independent control interfaces
The right side of the slide states that the XPO MSA will define an entirely new liquid-cooled pluggable form factor supporting 64 high-speed electrical lanes, covering multiple optical architectures including DR, FR, LR, SR and ZR. The exploded view labels the housing and pull tab, cold plate and standoffs, top and bottom paddle cards, and liquid inlet/outlet — this is a form factor that assumes liquid cooling from day one.
Worth reading alongside this: Larikova isn't wholly optimistic about XPO. Discussing another approach, she said something pointed — that certain solutions "only work in liquid-cooled environments," look elegant at first, but are hard to keep scaling, whether in terms of heat or density, and are in some sense another dead end. This is a product leader who has to place several bets at once and stays skeptical of every one of them.
8. The Closing Line: The Industry Must Decide Now
During Q&A, someone asked her which part is hardest to scale at these rates.
Her answer was direct: the hardest part is baud rate — the interconnect. Going from 260 GBd to 520 GBd is impossible, which means more than one path is needed. Her second point is one Taiwan's supply chain should take to heart: silicon germanium (SiGe) is the base material we use for TIAs and some drivers, and that's where the most progress is happening right now.
That lines up exactly with Ciena's remarks the same day about Vesta 200 using a SiGe EIC. Two companies with different architectural positions gave the same answer to "what is the key material for this generation."
And her conclusion was a request, not a prediction: the industry has to make choices now. If we don't stand up as an industry and say "LPO is it," we won't converge, and we'll keep redeveloping the same set of applications in every environment.
9. What It Means for Taiwan's Supply Chain
First, the dividend of short-reach IMDD is being eroded by time. On that reach chart, IMDD collapsed from 30 km to 1 km in just three generations. Optical module makers, TOSA/ROSA makers and the associated driver and TIA suppliers betting on the DR/FR/LR segment need to seriously confront the question of "how much room is left for this product line after 1.6T." The answer isn't zero — in-rack and campus interconnect from 500 m to 2 km is still enormous in volume — but the steepest part of the growth curve is moving to coherent lite.
Second, SiGe is the hidden winner of this generation. On the same day, Nokia and Ciena each named SiGe as the base material for TIAs and drivers, and the area seeing the fastest progress. That's a clear signal for players with SiGe process or related packaging and test capacity, and a reminder for those focused only on advanced CMOS nodes: this generation's differentiation isn't all on the digital side.
Third, liquid cooling is going from a nice-to-have to the price of entry. XPO's exploded view has a cold plate, standard standoffs and liquid inlet/outlet; Ciena's Open CPX mechanical drawing has a cold-plate contact area. Both companies' next-generation flagship form factors assume liquid cooling. Connectors, cold plates, tubing, quick disconnects, leak detection — this whole set of items once filed under "mechanical parts" is becoming part of the optical module BOM. Taiwan's manufacturing density here is an advantage, but only if suppliers follow the MSA mechanical specs now, rather than waiting for module makers to place orders.
Fourth, those Undefined cells are both an opportunity and a trap. Blanks on the 3.2T standards map mean whoever builds a solution first has a chance to get their approach written in; but they also mean molds and fixtures invested in now have a real chance of being scrapped once the standards land. Larikova's own situation is the best illustration — she has to build four form factors at once because she doesn't know which will win. What the supply chain can do isn't guess, but thicken the shared layers (mechanics, thermal, connectors, test) and thin out the bets.
10. Summary
The most honest thing about this talk is that it didn't sell any single path.
Nokia has OSFP, OSFP-XD, XPO, ELSFP 2.0, a double-sided pluggable media converter and a full-band sled — six form factors, because no single one covers every application. That isn't a rich product portfolio; it's forced risk diversification. And the cost of that diversification ultimately lands on the entire supply chain in the form of new molds, new qualification and new firmware every generation.
That IMDD reach-collapse chart and those Undefined cells are really saying the same thing: technology convergence can't keep up with the pace of speed increases. Until that gap closes, every component maker is building several versions at once, and every version dilutes engineering resources that could have been concentrated.
So her final request wasn't a technical one but a governance one: the industry needs to stand up and finish making its choices. In the 1600G generation, making a choice has become more important than making the best product.
Related Reading
ECOC 2026 Workshop: Fast-Narrow vs. Slow-Wide at 448G: the standards split discussed here has an earlier-stage version in 448G lane design
ECOC 2026 Light Sources Workshop: Lasers and Packaging Are the Real Bottleneck: beyond DSP power, the cost and yield pressure on the light-source side
Scale-Up Optics: The Fast-Narrow vs. Slow-Wide Trade-Off: the design split as in-rack interconnect moves from all-copper to partly optical
This article is for technology and industry trend analysis only and does not constitute investment advice.
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