OFC 2026 - A Key Step Toward 1.6 Tbps Silicon-Based NPO: Berxel Photonics Unveils a 940nm Back-Emitting VCSEL with an Integrated Metalens

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At OFC 2026, paper W1B.5, presented in person by Berxel Photonics CEO Connie Chang-Hasnain, opened a fresh technical path for optical interconnect in AI scale-up network architectures. As AI compute clusters impose ever stricter demands on bandwidth density and power efficiency, conventional pluggable modules are gradually giving way to near-packaged optics (NPO) and co-packaged optics (CPO). Berxel's 940-nm flip-chip back-emitting VCSEL technology, by integrating a metalens, tackles two major pain points of high-density packaging: heat dissipation and alignment tolerance.

Core Technology: HCG Metalens and the Back-Emitting Architecture

Conventional VCSELs are mostly top-emitting, with the electrodes and emission aperture on the same side, which limits thermal efficiency and the scalability of 2D arrays. Berxel's back-emitting architecture, combined with flip-chip packaging, brings the active region much closer to the submount for heat sinking.

The heart of the technology is the high-contrast grating (HCG) metalens integrated on the back of the substrate:

Very high alignment tolerance: experimental data show a radial tolerance of +/- 22 um and a longitudinal tolerance of up to 400 um. This is critical for automated, high-volume assembly of NPO/CPO modules and can significantly lower assembly cost.
Miniaturized beam shaping: the lithographically defined metalens is only about 40 µm in diameter and precisely confines the divergence angle to about 5° (at 8 mA), coupling directly into multimode fiber (MMF).

Reading the Data: Thermal Advantage and Measured 1.6 Tbps Performance

1. Extreme Thermal Performance: Junction Temperature ~40 degC Lower

Addressing the high-temperature challenge of AI compute environments, Berxel showed the decisive thermal-management advantage of the 940-nm back-emitting VCSEL. Compared with a conventional 850-nm top-emitting device at a 9 mA bias current, its junction temperature (Tj) is about ~40 degC lower.

Operating limits: the technology has achieved error-free 25G NRZ transmission at an extreme 140 degC and maintains clean 106G PAM4 eye diagrams at 110 degC. This means AI systems can use simpler cooling schemes and cut total system power.

2. 106 Gbps Per Lane and a 1.6 Tbps Array Demo

Berxel demonstrated a 1.6 Tbps NPO demo module built on this VCSEL:

Single-lane performance: each channel reaches 106 Gbps PAM4 over 30 m of OM2 fiber, with BER well below the IEEE 802.3db KP4-FEC threshold of 2.4E-4.
Module integration: the demo module integrates 15 channels (2 x 8 array) at 106 Gbps each, for a total bandwidth of 1.6 Tbps.

Metric	Measured Value	Industry Significance
Per-lane rate	106 Gbps PAM4	Matches today's mainstream 800G/1.6T requirements
Junction temperature delta	~- 40degC (vs 850 nm)	Greatly improves device lifetime and high-temperature reliability
Radial coupling tolerance	+/- 22 um	Relaxes NPO packaging precision and raises yield
Expected power	Approaching 1 pJ/bit	Meets CPO's demand for extreme energy efficiency

Simple Tech Trend's View: 940nm Back-Emission Will Become the VCSEL's "Second Curve"

Berxel's announcement marks an important turning point for VCSELs in data center interconnect.

Less reliance on DSP: because NPO/CPO architectures shorten the electrical path, Berxel's solution emphasizes eliminating part of the DSP requirement, achieving ultra-low power and ultra-high bandwidth density (> 1 Tbps/mm).
A clear cost path: by staying compatible with standard MMF (such as OM2) and leveraging mature, high-volume 2D VCSEL array production, Berxel expects packaging cost to fall below 100/Tbps.
The 200G future: the end of the presentation revealed early 200 Gbps PAM4 results (3 dB bandwidth of 41.4 GHz), with samples expected in June 2026.

In short, while the market still debates whether silicon photonics (SiPh) will fully replace VCSELs, Berxel has shown that with the one-two punch of "back emission + metalens," VCSELs retain irreplaceable cost and thermal advantages in short-reach AI compute networks at 1.6T and even 3.2T.