OFC 2026 - Entering the 200G/Lane Era: STMicroelectronics Unveils PIC100, Its 300mm Backside-Integrated Silicon Photonics Platform - STMicroelectronics (ST)

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Squeezed by both the AI compute revolution and the explosion of data center traffic, conventional electrical transmission can no longer sustain its power efficiency once the "rate × distance" product passes the critical point of 100 Gbps·m. At OFC 2026, STMicroelectronics presented its innovative PIC100 technology platform. This is not just an R&D prototype but a 300mm silicon photonics (SiPh) integration solution already in volume production, targeting 800G FR4 and future 1.6T applications.

Core Technology: The Strategic Significance of Backside Integration

Sébastien Crémer of STMicroelectronics pointed out that the biggest bottleneck facing 200G/lane, and eventually 400G/lane, applications is how to achieve efficient edge coupling and high-performance active device integration at the same time.

Breaking the Physical Limit of the 3um BOX

Conventional SOI substrate suppliers typically cannot provide a buried oxide (BOX) layer thicker than 3um, which causes the optical field to leak into the substrate (substrate leakage). Through its patented backside integration flow, ST's PIC100 creates an optical isolation layer of about 5um, eliminating the leakage problem entirely.

The Essence of Double-Sided Processing: Frontside + Backside

PIC100 production is split into two key stages:

Frontside processing: Three types of silicon waveguides (medium rib, deep rib, strip) are defined on 300nm SOI, integrated with high-speed germanium (Ge) photodiodes, modulators, and TiN heaters.
Backside processing: Using wafer bonding and thinning, 400nm silicon nitride (SiN) waveguides and edge couplers are integrated on the backside, along with a thick copper redistribution layer (RDL) to optimize electrical performance.

Key Metrics: Leading Performance Across the Board

PIC100 demonstrates the capability to support next-generation optical modules across every core metric:

1. Ultra-High-Bandwidth Active Devices

Ge photodiode: Achieves an impressive 80GHz bandwidth at -1V bias, with 1.0 A/W responsivity and only 11nA dark current. This is critical for receiving 200G PAM4 signals.
Deep rib modulator: Optimized for 200G/lane, with 50GHz bandwidth and a phase shift efficiency of 24.6 deg/mm at 1.8V.

2. Ultra-Low-Loss Waveguides and Coupling

Silicon waveguide loss: only 0.6dB/cm.
Edge coupler: Uses a 6-waveguide structure to reduce the impact of geometric variation. Measured total loss is <1dB for both TE and TM polarizations (typically 0.5–0.6dB).
SiN waveguide advantages: SiN has a far lower thermo-optic coefficient than silicon, so when integrating the demux required for FR applications, PIC100's SiN waveguides deliver excellent athermal performance, with O-band and C-band losses comparable to silicon waveguides.

Supply Chain Impact and Market Landscape

ST's PIC100 is more than a technology showcase; its commercial plans reveal its ambition:

Production and capacity: The technology has already entered volume production, and ST plans to increase capacity 4x by 2027.
Packaging compatibility: Beyond today's pluggable optical modules, PIC100 was designed from the outset with NPO/CPO requirements in mind, leaving room to integrate through-silicon vias (TSVs).

For module makers, PIC100 offers a highly integrated platform that can combine 800G FR4 TX and RX functions on a single chip, simplifying supply chain management and lowering packaging cost.

Simple Tech Trend's View: The Perfect Pairing of SiN and Backside Processing

The PIC100 that STMicroelectronics unveiled represents deep vertical integration of silicon photonics process technology. At STT, we see three highlights:

The pivotal role of SiN: SiN was long seen as a supporting material, but ST has used its athermal properties to solve the demux stability pain point in FR products, which will help it stand out against other SiPh platforms.
Solving the packaging bottleneck: Keeping edge coupler loss below 1dB is the ticket for silicon photonics to move into large-scale CPO packaging.
The 300mm scale advantage: Compared with legacy 200mm (8-inch) processes, 300mm (12-inch) wafers offer better uniformity and lower unit cost.